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 P RE L I M I NA R Y
LM3S102 Microcontroller
D ATA SHE E T
DS -LM3S 102- 04
C opyr ight (c) 2006 Lumi nary Micro , Inc.
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright (c) 2006 Luminary Micro, Inc. All rights reserved. Stellaris and the Luminary Micro logo are trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 2499 South Capital of Texas Hwy, Suite A-100 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com
2 Preliminary
October 6, 2006
LM3S102 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2 Revision History ............................................................................................................................. 15 About This Document..................................................................................................................... 16
Audience........................................................................................................................................................... 16 About This Manual............................................................................................................................................ 16 Related Documents .......................................................................................................................................... 16 Documentation Conventions............................................................................................................................. 16
1.
1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.5
Architectural Overview ....................................................................................................... 19
Product Features ................................................................................................................................. 19 Target Applications .............................................................................................................................. 22 High-Level Block Diagram ................................................................................................................... 23 Functional Overview ............................................................................................................................ 24 ARM CortexTM-M3 ............................................................................................................................... 24 Motor Control Peripherals .................................................................................................................... 24 Analog Peripherals .............................................................................................................................. 24 Serial Communications Peripherals..................................................................................................... 25 System Peripherals.............................................................................................................................. 26 Memory Peripherals............................................................................................................................. 27 Additional Features .............................................................................................................................. 27 Hardware Details ................................................................................................................................. 28 System Block Diagram ........................................................................................................................ 29
2.
2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 30
Block Diagram ..................................................................................................................................... 31 Functional Description ......................................................................................................................... 31 Serial Wire and JTAG Debug .............................................................................................................. 31 Embedded Trace Macrocell (ETM) ...................................................................................................... 32 Trace Port Interface Unit (TPIU) .......................................................................................................... 32 ROM Table .......................................................................................................................................... 32 Memory Protection Unit (MPU) ............................................................................................................ 32 Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 32
3. 4. 5.
5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.4 5.4.1 5.4.2
Memory Map ........................................................................................................................ 33 Interrupts ............................................................................................................................. 35 JTAG Interface .................................................................................................................... 38
Block Diagram ..................................................................................................................................... 39 Functional Description ......................................................................................................................... 39 JTAG Interface Pins............................................................................................................................. 40 JTAG TAP Controller ........................................................................................................................... 41 Shift Registers ..................................................................................................................................... 42 Operational Considerations ................................................................................................................. 42 Initialization and Configuration............................................................................................................. 43 Register Descriptions........................................................................................................................... 44 Instruction Register (IR) ....................................................................................................................... 44 Data Registers ..................................................................................................................................... 46
6.
6.1 6.1.1
System Control.................................................................................................................... 48
Functional Description ......................................................................................................................... 48 Device Identification............................................................................................................................. 48
October 6, 2006 Preliminary
3
Table of Contents
6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4
Reset Control ....................................................................................................................................... 48 Power Control ...................................................................................................................................... 51 Clock Control ....................................................................................................................................... 51 System Control .................................................................................................................................... 53 Initialization and Configuration............................................................................................................. 54 Register Map ....................................................................................................................................... 54 Register Descriptions........................................................................................................................... 55
7.
7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5
Internal Memory .................................................................................................................. 86
Block Diagram ..................................................................................................................................... 86 Functional Description ......................................................................................................................... 86 SRAM Memory .................................................................................................................................... 86 Flash Memory ...................................................................................................................................... 87 Initialization and Configuration............................................................................................................. 88 Changing Flash Protection Bits ........................................................................................................... 88 Flash Programming ............................................................................................................................. 89 Register Map ....................................................................................................................................... 89 Register Descriptions........................................................................................................................... 90
8.
8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.4 8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 100
Block Diagram ................................................................................................................................... 101 Functional Description ....................................................................................................................... 101 Data Register Operation .................................................................................................................... 102 Data Direction .................................................................................................................................... 103 Interrupt Operation............................................................................................................................. 103 Mode Control ..................................................................................................................................... 104 Pad Configuration .............................................................................................................................. 104 Identification....................................................................................................................................... 104 Initialization and Configuration........................................................................................................... 104 Register Map ..................................................................................................................................... 106 Register Descriptions......................................................................................................................... 107
9.
9.1 9.2 9.2.1 9.2.2 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4 9.5
General-Purpose Timers .................................................................................................. 138
Block Diagram ................................................................................................................................... 139 Functional Description ....................................................................................................................... 139 GPTM Reset Conditions .................................................................................................................... 139 32-Bit Timer Operating Modes........................................................................................................... 140 16-Bit Timer Operating Modes........................................................................................................... 141 Initialization and Configuration........................................................................................................... 145 32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 145 32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 146 16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 146 16-Bit Input Edge Count Mode .......................................................................................................... 146 16-Bit Input Edge Timing Mode ......................................................................................................... 147 16-Bit PWM Mode.............................................................................................................................. 147 Register Map ..................................................................................................................................... 148 Register Descriptions......................................................................................................................... 149
10.
10.1 10.2 10.3 10.4
Watchdog Timer ................................................................................................................ 170
Block Diagram ................................................................................................................................... 170 Functional Description ....................................................................................................................... 171 Initialization and Configuration........................................................................................................... 171 Register Map ..................................................................................................................................... 171
4 Preliminary
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LM3S102 Data Sheet
10.5
Register Descriptions......................................................................................................................... 172
11.
11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.3 11.4 11.5
Universal Asynchronous Receiver/Transmitter (UART)................................................ 193
Block Diagram ................................................................................................................................... 194 Functional Description ....................................................................................................................... 194 Transmit/Receive Logic ..................................................................................................................... 194 Baud-Rate Generation ....................................................................................................................... 195 Data Transmission ............................................................................................................................. 196 FIFO Operation .................................................................................................................................. 196 Interrupts............................................................................................................................................ 196 Loopback Operation .......................................................................................................................... 197 Initialization and Configuration........................................................................................................... 197 Register Map ..................................................................................................................................... 198 Register Descriptions......................................................................................................................... 199
12.
12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.3 12.4 12.5
Synchronous Serial Interface (SSI) ................................................................................. 229
Block Diagram ................................................................................................................................... 229 Functional Description ....................................................................................................................... 230 Bit Rate Generation ........................................................................................................................... 230 FIFO Operation .................................................................................................................................. 230 Interrupts............................................................................................................................................ 230 Frame Formats .................................................................................................................................. 231 Initialization and Configuration........................................................................................................... 238 Register Map ..................................................................................................................................... 239 Register Descriptions......................................................................................................................... 240
13.
13.1 13.2 13.2.1 13.2.2 13.3 13.4 13.5 13.6
Inter-Integrated Circuit (I2C) Interface ............................................................................ 264
Block Diagram ................................................................................................................................... 264 Functional Description ....................................................................................................................... 264 I2C Bus Functional Overview ............................................................................................................. 265 Available Speed Modes ..................................................................................................................... 272 Initialization and Configuration........................................................................................................... 273 Register Map ..................................................................................................................................... 273 Register Descriptions (I2C Master).................................................................................................... 274 Register Descriptions (I2C Slave)...................................................................................................... 288
14.
14.1 14.2 14.2.1 14.3 14.4 14.5
Analog Comparator........................................................................................................... 296
Block Diagram ................................................................................................................................... 296 Functional Description ....................................................................................................................... 296 Internal Reference Programming....................................................................................................... 297 Initialization and Configuration........................................................................................................... 298 Register Map ..................................................................................................................................... 299 Register Descriptions......................................................................................................................... 299
15. 16. 17. 18.
18.1 18.1.1 18.1.2 18.1.3 18.1.4
Pin Diagram ....................................................................................................................... 307 Signal Tables ..................................................................................................................... 308 Operating Characteristics ................................................................................................ 315 Electrical Characteristics ................................................................................................. 316
DC Characteristics ............................................................................................................................. 316 Maximum Ratings .............................................................................................................................. 316 Recommended DC Operating Conditions ......................................................................................... 316 On-Chip Low Drop-Out (LDO) Regulator Characteristics .................................................................. 317 Power Specifications ......................................................................................................................... 318
October 6, 2006 Preliminary
5
Table of Contents
18.1.5 18.2 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 18.2.8
Flash Memory Characteristics ........................................................................................................... 318 AC Characteristics ............................................................................................................................. 319 Load Conditions ................................................................................................................................. 319 Clocks ................................................................................................................................................ 319 Analog Comparator............................................................................................................................ 320 I2C...................................................................................................................................................... 320 Synchronous Serial Interface (SSI) ................................................................................................... 322 JTAG and Boundary Scan ................................................................................................................. 324 General-Purpose I/O.......................................................................................................................... 326 Reset ................................................................................................................................................. 326
19.
A.1 A.1.1 A.1.2 A.2 A.2.1 A.2.2 A.2.3 A.3 A.3.1 A.3.2 A.3.3 A.3.4 A.3.5 A.3.6
Package Information......................................................................................................... 329
Interfaces ........................................................................................................................................... 330 UART ................................................................................................................................................. 330 SSI ..................................................................................................................................................... 330 Packet Handling................................................................................................................................. 330 Packet Format ................................................................................................................................... 331 Sending Packets ................................................................................................................................ 331 Receiving Packets ............................................................................................................................. 331 Commands ........................................................................................................................................ 331 COMMAND_PING (0x20) .................................................................................................................. 332 COMMAND_GET_STATUS (0x23) ................................................................................................... 332 COMMAND_DOWNLOAD (0x21)...................................................................................................... 332 COMMAND_SEND_DATA (0x24) ..................................................................................................... 332 COMMAND_RUN (0x22) ................................................................................................................... 333 COMMAND_RESET (0x25)............................................................................................................... 333
Appendix A. Serial Flash Loader.................................................................................................. 330
Ordering and Contact Information .............................................................................................. 334
Ordering Information ....................................................................................................................................... 334 Development Kit ............................................................................................................................................. 334 Company Information ..................................................................................................................................... 334 Support Information ........................................................................................................................................ 335
6 Preliminary
October 6, 2006
LM3S102 Data Sheet
List of Figures
Figure 1-1. Figure 1-2. Figure 2-1. Figure 2-2. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 11-1. Figure 11-2. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. Figure 12-11. Figure 12-12. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Stellaris High-Level Block Diagram ........................................................................................... 23 LM3S102 Controller System-Level Block Diagram ................................................................... 29 CPU Block Diagram .................................................................................................................. 31 TPIU Block Diagram .................................................................................................................. 32 JTAG Module Block Diagram .................................................................................................... 39 Test Access Port State Machine ............................................................................................... 42 IDCODE Register Format.......................................................................................................... 46 BYPASS Register Format ......................................................................................................... 46 Boundary Scan Register Format ............................................................................................... 47 External Circuitry to Extend Reset............................................................................................. 49 Main Clock Tree ........................................................................................................................ 52 Flash Block Diagram ................................................................................................................. 86 GPIO Module Block Diagram .................................................................................................. 101 GPIO Port Block Diagram........................................................................................................ 102 GPIODATA Write Example...................................................................................................... 103 GPIODATA Read Example ..................................................................................................... 103 GPTM Module Block Diagram ................................................................................................. 139 16-Bit Input Edge Count Mode Example ................................................................................. 143 16-Bit Input Edge Time Mode Example................................................................................... 144 16-Bit PWM Mode Example .................................................................................................... 145 WDT Module Block Diagram ................................................................................................... 170 UART Module Block Diagram.................................................................................................. 194 UART Character Frame........................................................................................................... 195 SSI Module Block Diagram...................................................................................................... 229 TI Synchronous Serial Frame Format (Single Transfer).......................................................... 231 TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 232 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 233 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 233 Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 234 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 234 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 235 Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 235 MICROWIRE Frame Format (Single Frame)........................................................................... 236 MICROWIRE Frame Format (Continuous Transfer) ............................................................... 237 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 238 I2C Block Diagram ................................................................................................................... 264 I2C Bus Configuration.............................................................................................................. 265 Data Validity During Bit Transfer on the I2C Bus..................................................................... 265 START and STOP Conditions ................................................................................................. 265 Complete Data Transfer with a 7-Bit Address ......................................................................... 266 R/S Bit in First Byte ................................................................................................................. 267 Master Single SEND................................................................................................................ 267 Master Single RECEIVE.......................................................................................................... 268 Master Burst SEND ................................................................................................................. 269 Master Burst RECEIVE ........................................................................................................... 270 Master Burst RECEIVE after Burst SEND............................................................................... 271
October 6, 2006 Preliminary
7
List of Figures
Figure 13-12. Figure 13-13. Figure 14-1. Figure 14-2. Figure 14-3. Figure 15-1. Figure 18-1. Figure 18-2. Figure 18-3. Figure 18-4. Figure 18-5. Figure 18-6. Figure 18-7. Figure 18-8. Figure 18-9. Figure 18-10. Figure 18-11. Figure 18-12. Figure 18-13. Figure 18-14. Figure 19-1.
Master Burst SEND after Burst RECEIVE............................................................................... 271 Slave Command Sequence..................................................................................................... 272 Analog Comparator Module Block Diagram ............................................................................ 296 Structure of Comparator Unit................................................................................................... 297 Comparator Internal Reference Structure ............................................................................... 298 Pin Connection Diagram.......................................................................................................... 307 Load Conditions....................................................................................................................... 319 I2C Timing................................................................................................................................ 321 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 322 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 323 SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 323 JTAG Test Clock Input Timing................................................................................................. 325 JTAG Test Access Port (TAP) Timing ..................................................................................... 325 JTAG TRST Timing ................................................................................................................. 325 External Reset Timing (RST)................................................................................................... 327 Power-On Reset Timing .......................................................................................................... 327 Brown-Out Reset Timing ......................................................................................................... 327 Software Reset Timing ............................................................................................................ 327 Watchdog Reset Timing .......................................................................................................... 328 LDO Reset Timing ................................................................................................................... 328 28-Pin SOIC Package ............................................................................................................. 329
8 Preliminary
October 6, 2006
LM3S102 Data Sheet
List of Tables
Table 1-1. Table 3-1. Table 4-1. Table 4-2. Table 5-1. Table 5-2. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 7-1. Table 7-2. Table 8-1. Table 8-2. Table 8-3. Table 9-1. Table 9-2. Table 10-1. Table 11-1. Table 12-1. Table 13-1. Table 13-2. Table 13-3. Table 14-1. Table 14-2. Table 14-3. Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 17-1. Table 17-2. Table 18-1. Table 18-2. Table 18-3. Table 18-4. Table 18-5. Table 18-6. Table 18-7. Table 18-8. Table 18-9. Table 18-10. Table 18-11. Table 18-12. Table 18-13. Table 18-14. Documentation Conventions ..................................................................................................... 16 Memory Map.............................................................................................................................. 33 Exception Types ........................................................................................................................ 35 Interrupts ................................................................................................................................... 36 JTAG Port Pins Reset State ...................................................................................................... 40 JTAG Instruction Register Commands ...................................................................................... 44 System Control Register Map.................................................................................................... 54 VADJ to VOUT .......................................................................................................................... 65 PLL Mode Control...................................................................................................................... 76 Default Crystal Field Values and PLL Programming ................................................................. 77 Flash Protection Policy Combinations ....................................................................................... 88 Flash Register Map ................................................................................................................... 89 GPIO Pad Configuration Examples ........................................................................................ 104 GPIO Interrupt Configuration Example ................................................................................... 105 GPIO Register Map ................................................................................................................. 106 16-Bit Timer With Prescaler Configurations ............................................................................ 142 GPTM Register Map................................................................................................................ 148 WDT Register Map .................................................................................................................. 171 UART Register Map ................................................................................................................ 198 SSI Register Map .................................................................................................................... 239 Examples of I2C Master Timer Period versus Speed Mode .................................................... 273 I2C Register Map ..................................................................................................................... 274 Write Field Decoding for I2CMCS[3:0] Field ........................................................................... 278 Comparator 0 Operating Modes .............................................................................................. 297 Internal Reference Voltage and ACREFCTL Field Values ...................................................... 298 Analog Comparator Register Map ........................................................................................... 299 Signals by Pin Number ............................................................................................................ 308 Signals by Signal Name .......................................................................................................... 310 Signals by Function, Except for GPIO ..................................................................................... 312 GPIO Pins and Alternate Functions......................................................................................... 313 Temperature Characteristics ................................................................................................... 315 Thermal Characteristics........................................................................................................... 315 Maximum Ratings.................................................................................................................... 316 Recommended DC Operating Conditions ............................................................................... 316 LDO Regulator Characteristics................................................................................................ 317 Power Specifications ............................................................................................................... 318 Flash Memory Characteristics ................................................................................................. 318 Phase Locked Loop (PLL) Characteristics .............................................................................. 319 Clock Characteristics............................................................................................................... 319 Analog Comparator Characteristics......................................................................................... 320 Analog Comparator Voltage Reference Characteristics.......................................................... 320 I2C Characteristics................................................................................................................... 320 SSI Characteristics .................................................................................................................. 322 JTAG Characteristics............................................................................................................... 324 GPIO Characteristics............................................................................................................... 326 Reset Characteristics .............................................................................................................. 326
October 6, 2006 Preliminary
9
List of Registers
List of Registers
System Control ............................................................................................................................... 48
Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 1: Register 2: Register 3: Register 4: Device Identification 0 (DID0), offset 0x000 .............................................................................. 56 Device Identification 1 (DID1), offset 0x004 .............................................................................. 57 Device Capabilities 0 (DC0), offset 0x008................................................................................. 59 Device Capabilities 1 (DC1), offset 0x010................................................................................. 60 Device Capabilities 2 (DC2), offset 0x014................................................................................. 61 Device Capabilities 3 (DC3), offset 0x018................................................................................. 62 Device Capabilities 4 (DC4), offset 0x01C ................................................................................ 63 Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................ 64 LDO Power Control (LDOPCTL), offset 0x034.......................................................................... 65 Software Reset Control 0 (SRCR0), offset 0x040 ..................................................................... 66 Software Reset Control 1 (SRCR1), offset 0x044 ..................................................................... 67 Software Reset Control 2 (SRCR2), offset 0x048 ..................................................................... 68 Raw Interrupt Status (RIS), offset 0x050................................................................................... 69 Interrupt Mask Control (IMC), offset 0x054 ............................................................................... 70 Masked Interrupt Status and Clear (MISC), offset 0x058.......................................................... 72 Reset Cause (RESC), offset 0x05C .......................................................................................... 73 Run-Mode Clock Configuration (RCC), offset 0x060................................................................. 74 XTAL to PLL Translation (PLLCFG), offset 0x064 .................................................................... 78 Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 ....................................................... 79 Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110..................................................... 79 Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120........................................... 79 Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 ....................................................... 80 Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114..................................................... 80 Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124........................................... 80 Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 ....................................................... 82 Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118..................................................... 82 Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128........................................... 82 Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .............................................. 83 Clock Verification Clear (CLKVCLR), offset 0x150.................................................................... 84 Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ....................................... 85 Flash Memory Protection Read Enable (FMPRE), offset 0x130 ............................................... 91 Flash Memory Protection Program Enable (FMPPE), offset 0x134 .......................................... 91 USec Reload (USECRL), offset 0x140...................................................................................... 92 Flash Memory Address (FMA), offset 0x000 ............................................................................. 93 Flash Memory Data (FMD), offset 0x004 .................................................................................. 94 Flash Memory Control (FMC), offset 0x008 .............................................................................. 95 Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ................................................... 97 Flash Controller Interrupt Mask (FCIM), offset 0x010 ............................................................... 98 Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014........................... 99 GPIO Data (GPIODATA), offset 0x000 ................................................................................... 108 GPIO Direction (GPIODIR), offset 0x400 ................................................................................ 109 GPIO Interrupt Sense (GPIOIS), offset 0x404......................................................................... 110 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408.............................................................. 111
Internal Memory .............................................................................................................................. 86
General-Purpose Input/Outputs (GPIOs) .................................................................................... 100
10 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 1: Register 2:
GPIO Interrupt Event (GPIOIEV), offset 0x40C....................................................................... 112 GPIO Interrupt Mask (GPIOIM), offset 0x410.......................................................................... 113 GPIO Raw Interrupt Status (GPIORIS), offset 0x414.............................................................. 114 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ........................................................ 115 GPIO Interrupt Clear (GPIOICR), offset 0x41C....................................................................... 116 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ................................................. 117 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500.............................................................. 118 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504.............................................................. 119 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508.............................................................. 120 GPIO Open Drain Select (GPIOODR), offset 0x50C............................................................... 121 GPIO Pull-Up Select (GPIOPUR), offset 0x510 ...................................................................... 122 GPIO Pull-Down Select (GPIOPDR), offset 0x514.................................................................. 123 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518...................................................... 124 GPIO Digital Input Enable (GPIODEN), offset 0x51C ............................................................. 125 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ........................................... 126 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ........................................... 127 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ........................................... 128 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC........................................... 129 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ........................................... 130 GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 ............................................ 131 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ........................................... 132 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC........................................... 133 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .............................................. 134 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .............................................. 135 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .............................................. 136 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC.............................................. 137 GPTM Configuration (GPTMCFG), offset 0x000..................................................................... 150 GPTM TimerA Mode (GPTMTAMR), offset 0x004 .................................................................. 151 GPTM TimerB Mode (GPTMTBMR), offset 0x008 .................................................................. 152 GPTM Control (GPTMCTL), offset 0x00C............................................................................... 153 GPTM Interrupt Mask (GPTMIMR), offset 0x018 .................................................................... 155 GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .......................................................... 157 GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ..................................................... 158 GPTM Interrupt Clear (GPTMICR), offset 0x024..................................................................... 159 GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ...................................................... 160 GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C...................................................... 161 GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ....................................................... 162 GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ....................................................... 163 GPTM TimerA Prescale (GPTMTAPR), offset 0x038.............................................................. 164 GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ............................................................. 165 GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040................................................ 166 GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044................................................ 167 GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................... 168 GPTM TimerB (GPTMTBR), offset 0x04C .............................................................................. 169 Watchdog Load (WDTLOAD), offset 0x000 ............................................................................ 173 Watchdog Value (WDTVALUE), offset 0x004 ......................................................................... 174
General-Purpose Timers .............................................................................................................. 138
Watchdog Timer............................................................................................................................ 170
October 6, 2006 Preliminary
11
List of Registers
Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 1: Register 2: Register 3: Register 4:
Watchdog Control (WDTCTL), offset 0x008............................................................................ 175 Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 176 Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 177 Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 178 Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 179 Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 180 Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 181 Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 182 Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 183 Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 184 Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 185 Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 186 Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 187 Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 188 Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 189 Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 190 Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 191 Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 192 UART Data (UARTDR), offset 0x000 ...................................................................................... 200 UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 202 UART Flag (UARTFR), offset 0x018 ....................................................................................... 204 UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 206 UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 207 UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 208 UART Control (UARTCTL), offset 0x030................................................................................. 210 UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 211 UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 212 UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 214 UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 215 UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 216 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 217 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 218 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 219 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 220 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 221 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 222 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 223 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 224 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 225 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 226 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 227 UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 228 SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 241 SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 243 SSI Data (SSIDR), offset 0x008 .............................................................................................. 245 SSI Status (SSISR), offset 0x00C ........................................................................................... 246
Universal Asynchronous Receiver/Transmitter (UART) ........................................................... 193
Synchronous Serial Interface (SSI) ............................................................................................. 229
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Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6:
SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 247 SSI Interrupt Mask (SSIIM), offset 0x014 ................................................................................ 248 SSI Raw Interrupt Status (SSIRIS), offset 0x018 .................................................................... 249 SSI Masked Interrupt Status (SSIMIS), offset 0x01C.............................................................. 250 SSI Interrupt Clear (SSIICR), offset 0x020.............................................................................. 251 SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0.................................................. 252 SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4.................................................. 253 SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8.................................................. 254 SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ................................................. 255 SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0.................................................. 256 SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4.................................................. 257 SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8.................................................. 258 SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ................................................. 259 SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0..................................................... 260 SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4..................................................... 261 SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8..................................................... 262 SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .................................................... 263 I2C Master Slave Address (I2CMSA), offset 0x000 ................................................................ 275 I2C Master Control/Status (I2CMCS), offset 0x004................................................................. 276 I2C Master Data (I2CMDR), offset 0x008................................................................................ 281 I2C Master Timer Period (I2CMTPR), offset 0x00C ................................................................ 282 I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ............................................................... 283 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ...................................................... 284 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ................................................ 285 I2C Master Interrupt Clear (I2CMICR), offset 0x01C ............................................................... 286 I2C Master Configuration (I2CMCR), offset 0x020 .................................................................. 287 I2C Slave Own Address (I2CSOAR), offset 0x000 .................................................................. 288 I2C Slave Control/Status (I2CSCSR), offset 0x004 ................................................................. 289 I2C Slave Data (I2CSDR), offset 0x008................................................................................... 291 I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ................................................................. 292 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010......................................................... 293 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014................................................... 294 I2C Slave Interrupt Clear (I2CSICR), offset 0x018 .................................................................. 295 Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00........................................ 300 Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04.............................................. 301 Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ................................................ 302 Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ............................ 303 Analog Comparator Status 0 (ACSTAT0), offset 0x20 ............................................................ 304 Analog Comparator Control 0 (ACCTL0), offset 0x24 ............................................................. 305
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 264
Analog Comparator ...................................................................................................................... 296
Pin Diagram ................................................................................................................................... 307
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List of Registers
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LM3S102 Data Sheet
Revision History
This table provides a summary of the document revisions.
Date March 27, 2006 March 30, 2006 Revision 00 01 Description Initial public release of LM3S101 and LM3S102 data sheets. Second release of LM3S101 and LM3S102 data sheets. Includes the following changes: * Added timing data. May 2006 02 Third release of LM3S101 and LM3S102 data sheets. Includes the following changes: * Added Initialization and Configuration section to System Control chapter * Renamed boot oscillator to internal oscillator * Corrected reset value of DC1 in System Control Register Map (was correct on register reference page) * Corrected description of bits to set to enable PWM mode in timer * Corrected WDTICR register offset (was correct in Register Map but not on register reference page) * Added Watchdog Test (WDTTEST) register * Changed I2CMMIS and I2CSMIS register types in I2C Register Map to be RO (was correct on register reference pages) * Changed some bit and register names for consistency with DriverLib: - Changed USESYS bit in RCC register to USESYSDIV - Changed name of Capture bit fields in GPTMIMR, GPTMRIS, GPTMMIS, and GPTMICR registers from C1bitname and C2bitname to CAbitname and CBbitname * Fixed minor style and edit issues July 2006 03 Fourth release of LM3S101 and LM3S102 data sheets. Includes the following changes: * Added initialization and configuration content into PWM, I2C, Comparators, and JTAG chapters. * Clarified that peripheral clock must be set before enabling peripherals in "Initialization and Configuration" sections. October 2006 04 Fifth release of LM3S102 data sheet. Includes the following changes: * Updated the clocking examples in the I2C chapter. * Added Serial Flash Loader usage information. * Added "5-V-tolerant" description for GPIOs to feature list, GPIO chapter, and Electrical chapter. * Added maximum values for 20 MHz and 25 MHz parts to Table 9-1, "16-Bit Timer With Prescaler Configurations" in the Timers chapter. * Made the following changes in the System Control chapter: - Updated field descriptions in the Run-Mode Clock Configuration (RCC) register . - Updated the internal oscillator clock speed. - Added the Deep-Sleep Clock Configuration (DSLPCFG) register. - Added bus fault information to the clock gating registers.
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About This Document
About This Document
This data sheet provides reference information for the LM3S102 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM(R) CortexTM-M3 core.
Audience
This manual is intended for system software developers, hardware designers, and application developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com: ARM(R) CortexTM-M3 Technical Reference Manual CoreSightTM Design Kit Technical Reference Manual ARM(R) v7-M Architecture Application Level Reference Manual The following related documents are also referenced: IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1-1. Table 1-1. Documentation Conventions
Notation General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1, and SRCR2. A single bit in a register. Two or more consecutive and related bits. A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 3-1, "Memory Map," on page 33. Meaning
bit bit field offset 0xnnn
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LM3S102 Data Sheet
Table 1-1.
Documentation Conventions
Notation Meaning Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. Register bits marked reserved are reserved for future use. Reserved bits return an indeterminate value, and should never be changed. Only write a reserved bit with its current value. The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. Software can read this field. Always write the chip reset value. Software can read or write this field. Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read.
Register N
reserved
yy:xx
Register Bit/Field Types RO R/W R/W1C
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data. This value in the register bit diagram shows the bit/field value after any reset, unless noted. Bit cleared to 0 on chip reset. Bit set to 1 on chip reset. Nondeterministic.
Register Bit/Field Reset Value 0 1 - Pin/Signal Notation [] pin signal
Pin alternate function; a pin defaults to the signal without the brackets. Refers to the physical connection on the package. Refers to the electrical signal encoding of a pin.
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About This Document
Table 1-1.
Documentation Conventions
Notation Meaning Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
assert a signal
deassert a signal SIGNAL
SIGNAL
Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. Binary numbers are indicated with a b suffix, for example, 1011b. Decimal numbers are written without a prefix or suffix.
0x
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1
Architectural Overview
The Luminary Micro StellarisTM family of microcontrollers--the first ARM(R) CortexTM-M3 based controllers--brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S102 controller in the Stellaris family offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the controller uses ARM's Thumb(R)-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Luminary Micro offers a complete solution to get to market quickly, with a customer development board, white papers and application notes, and a strong support, sales, and distributor network.
1.1
Product Features
The LM3S102 microcontroller includes the following product features: 32-Bit RISC Performance - 32-bit ARM(R) CortexTM-M3 v7M architecture optimized for small-footprint embedded applications - Thumb(R)-compatible Thumb-2-only instruction set processor core for high code density - 20-MHz operation - Hardware-division and single-cycle-multiplication - Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling - 14 interrupts with eight priority levels - Unaligned data access, enabling data to be efficiently packed into memory - Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control Internal Memory - 8 KB single-cycle flash * * * User-managed flash block protection on a 2-KB block basis User-managed flash data programming User-defined and managed flash-protection block
- 2 KB single-cycle SRAM General-Purpose Timers - Two timers, each of which can be configured as a single 32-bit timer or as two 16-bit timers - 32-bit Timer modes: * * * * Programmable one-shot timer Programmable periodic timer Real-Time Clock when using an external 32.768-KHz clock as the input User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug
- 16-bit Timer modes:
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Architectural Overview
* * * * * * *
General-purpose timer function with an 8-bit prescaler Programmable one-shot timer Programmable periodic timer User-enabled stalling when the controller asserts CPU Halt flag during debug Input edge count capture Input edge time capture Simple PWM mode with software-programmable output inversion of the PWM signal
- 16-bit Input Capture modes:
- 16-bit PWM mode: ARM FiRM-compliant Watchdog Timer - 32-bit down counter with a programmable load register - Separate watchdog clock with an enable - Programmable interrupt generation logic with interrupt masking - Lock register protection from runaway software - Reset generation logic with an enable/disable - User-enabled stalling when the controller asserts the CPU Halt flag during debug Synchronous Serial Interface (SSI) - Master or slave operation - Programmable clock bit rate and prescale - Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep - Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces - Programmable data frame size from 4 to 16 bits - Internal loopback test mode for diagnostic/debug testing UART - Fully programmable 16C550-type UART - Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading - Programmable baud-rate generator with fractional divider - Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface - FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 - Standard asynchronous communication bits for start, stop, and parity - False-start-bit detection - Line-break generation and detection Analog Comparator - Configurable for output to drive an output pin or generate an interrupt
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- Compare external pin input to external pin input or to internal programmable voltage reference I2C - Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode - Interrupt generation - Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode GPIOs - Up to 18 GPIOs, depending on configuration - 5-V-tolerant input/outputs - Programmable interrupt generation as either edge-triggered or level-sensitive - Bit masking in both read and write operations through address lines - Programmable control for GPIO pad configuration: * * * * * Power - On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V - Low-power options on controller: Sleep and Deep-sleep modes - Low-power options for peripherals: software controls shutdown of individual peripherals - User-enabled LDO unregulated voltage detection and automatic reset - 3.3-V supply brownout detection and reporting via interrupt or reset Flexible Reset Sources - Power-on reset (POR) - Reset pin assertion - Brown-out (BOR) detector alerts to system power drops - Software reset - Watchdog timer reset - Internal low drop-out (LDO) regulator output goes unregulated Additional Features - Six reset sources - Programmable clock source control - Clock gating to individual peripherals for power savings - IEEE 1149.1-1990 compliant Test Access Port (TAP) controller Weak pull-up or pull-down resistors 2-mA, 4-mA, and 8-mA pad drive Slew rate control for the 8-mA drive Open drain enables Digital input enables
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Architectural Overview
- Debug access via JTAG and Serial Wire interfaces - Full JTAG boundary scan Industrial-range 28-pin RoHS-compliant SOIC package
1.2
Target Applications
Factory automation and control Industrial control power devices Building and home automation Stepper motors
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LM3S102 Data Sheet
1.3
High-Level Block Diagram
Figure 1-1. Stellaris High-Level Block Diagram
ARM Cortex-M3 (including Nested DCode bus Flash Vectored Interrupt Controller (NVIC)) ICode bus
Memory Peripherals
System Control & Clocks
LMI JTAG Test Access Port (TAP) Controller
APB Bridge
SRAM
General-Purpose Timers General-Purpose Input/Outputs (GPIOs) Watchdog Timer
System Peripherals
Peripheral Bus
Universal Asynchronous Receiver/ Transmitter (UART) Inter Integrated Circuit (I2C)
Synchronous Serial Serial Communications Interface Peripherals (SSI)
Analog Comparator
Analog Peripherals
LM3S102
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Architectural Overview
1.4
Functional Overview
The following sections provide an overview of the features of the LM3S102 microcontroller. The chapter number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in "Ordering and Contact Information" on page 334.
1.4.1
1.4.1.1
ARM CortexTM-M3
Processor Core (Section 2 on page 30) All members of the Stellaris product family, including the LM3S102 microcontroller, are designed around an ARM CortexTM-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Section 2, "ARM Cortex-M3 Processor Core," on page 30 provides an overview of the ARM core; the core is detailed in the ARM(R) CortexTM-M3 Technical Reference Manual.
1.4.1.2
Nested Vectored Interrupt Controller (NVIC) The LM3S102 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 14 interrupts. Section 4, "Interrupts," on page 35 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM(R) CortexTM-M3 Technical Reference Manual.
1.4.2
Motor Control Peripherals
To enhance motor control, the LM3S102 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1
PWM ("16-Bit PWM Mode" on page 147) Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. On the LM3S102, PWM motion control functionality can be achieved through the motion control features of the general-purpose timers (using the CCP pins). The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3
1.4.3.1
Analog Peripherals
To handle analog signals, the LM3S102 controller offers an analog comparator. Analog Comparator (Section 14 on page 296) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result.
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The LM3S102 controller provides one analog comparator that can be configured to drive an output or generate an interrupt. A comparator can compare a test voltage against any one of these voltages: An individual external reference voltage A shared single external reference voltage A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. The interrupt generation logic is separate.
1.4.4
Serial Communications Peripherals
The LM3S102 controller supports both asynchronous and synchronous serial communications with one fully programmable 16C550-type UART, SSI and I2C serial communications.
1.4.4.1
UART (Section 11 on page 193) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S102 controller includes one fully programmable 16C550-type UART that supports data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not register compatible.) Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked.
1.4.4.2
SSI (Section 12 on page 229) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface. The Stellaris SSI module provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3
I2C (Section 13 on page 264) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL).
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Architectural Overview
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The Stellaris I2C module provides the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master.
1.4.5
1.4.5.1
System Peripherals
Programmable GPIOs (Section 8 on page 100) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is composed of three physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports up to 18 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see Table 16-4 on page 313 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines.
1.4.5.2
Two Programmable Timers (Section 9 on page 138) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM block provides two 16-bit timer/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). When configured in 32-bit mode, a timer can run as a one-shot timer, periodic timer, or Real-Time Clock (RTC). When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation.
1.4.5.3
Watchdog Timer (Section 10 on page 170) A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered.
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1.4.6
1.4.6.1
Memory Peripherals
The Stellaris controllers offer both SRAM and Flash memory. SRAM (Section 7.2.1 on page 86) The LM3S102 static random access memory (SRAM) controller supports 2 KB SRAM. The internal SRAM of the Stellaris devices is located at address 0x20000000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation.
1.4.6.2
Flash (Section 7.2.2 on page 87) The LM3S102 Flash controller supports 8 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger.
1.4.7
1.4.7.1
Additional Features
Memory Map (Section 3 on page 33) A memory map lists the location of instructions and data in memory. The memory map for the LM3S102 controller can be found on page 33. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The ARM(R) CortexTM-M3 Technical Reference Manual provides further information on the memory map.
1.4.7.2
JTAG TAP Controller (Section 5 on page 38) The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. The JTAG port provides a high degree of testability and chip-level access at a low cost. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. The multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for the ARM, LMI, and unimplemented JTAG instructions.
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Architectural Overview
1.4.7.3
System Control and Clocks (Section 6 on page 48) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting.
1.4.8
Hardware Details
Details on the pins and package can be found in the following sections: Section 15, "Pin Diagram," on page 307 Section 16, "Signal Tables," on page 308 Section 17, "Operating Characteristics," on page 315 Section 18, "Electrical Characteristics," on page 316 Section 19, "Package Information," on page 329
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1.5
System Block Diagram
Figure 1-2. LM3S102 Controller System-Level Block Diagram
VDD_3.3V LDO GND ARM Cortex-M3 (20 MHz) CM3Core NVIC Debug OSC0 OSC1 POR BOR System Control & Clocks
Peripheral Bus
LDO
VDD_2.5V
DCode ICode Flash (8 KB)
Bus
IOSC
PLL APB Bridge SRAM (2 KB)
Watchdog Timer
RST
GPIO Port A
GPIO Port B PB7/TRST Analog Comparators Master Slave PB6/CCP1/C0+ PB5/C0o PB4/C0PB3/I2CSDA PB2/I2CSCL
PA5/SSITx PA4/SSIRx PA3/SSIFss PA2/SSIClk PA1/U0Tx PA0/U0Rx
SSI I2C UART0 GP Timer1 GPIO Port C
PB1/32KHz
GP Timer0 PC3/TDO/SWO PC2/TDI PC1/TMS/SWDIO PC0/TCK/SWCLK JTAG SWD/SWO
PB0/CCP0
LM3S102
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ARM Cortex-M3 Processor Core
2
ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: Compact core. Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. Full-featured debug solution with a: - Serial Wire JTAG Debug Port (SWJ-DP) - Flash Patch and Breakpoint (FPB) unit for implementing breakpoints - Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling - Instrumentation Trace Macrocell (ITM) for support of printf style debugging - Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. For more information on the ARM Cortex-M3 processor core, see the ARM(R) CortexTM-M3 Technical Reference Manual. For information on SWJ-DP, see the CoreSightTM Design Kit Technical Reference Manual.
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2.1
Block Diagram
Figure 2-1. CPU Block Diagram
Nested Vectored Interrupt Controller
Interrupts Sleep Debug Instructions Data Trace Port Interface Unit CM3 Core
ARM Cortex-M3
Serial Wire Output Trace Port (SWO)
Flash Patch and Breakpoint
Data Watchpoint and Trace
Instrumentation Trace Macrocell
Private Peripheral Bus (external) ROM Table
Private Peripheral Bus (internal ) Bus Matrix
Adv. Peripheral Bus I-code bus D-code bus System bus
Serial Wire JTAG Debug Port
Adv. HighPerf. Bus Access Port
2.2
Functional Description
Important: The ARM(R) CortexTM-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. This section describes the Stellaris implementation. Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1. As noted in the ARM(R) CortexTM-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1
Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSightTM-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, "Debug Port," of the ARM(R) CortexTM-M3 Technical Reference Manual does not apply to Stellaris devices. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSightTM Design Kit Technical Reference Manual for details on SWJ-DP.
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ARM Cortex-M3 Processor Core
2.2.2
Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM(R) CortexTM-M3 Technical Reference Manual can be ignored.
2.2.3
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2. This is similar to the non-ETM version described in the ARM(R) CortexTM-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram
Debug ATB Slave Port
ATB Interface
Asynchronous FIFO
Trace Out (serializer)
Serial Wire Trace Port (SWO)
APB Slave Port
APB Interface
2.2.4
ROM Table
The default ROM table was implemented as described in the ARM(R) CortexTM-M3 Technical Reference Manual.
2.2.5
Memory Protection Unit (MPU)
The LM3S102 controller does not include the memory protection unit (MPU) of the ARM CortexM3.
2.2.6
2.2.6.1
Nested Vectored Interrupt Controller (NVIC)
Interrupts The ARM(R) CortexTM-M3 Technical Reference Manual describes the maximum number of interrupts and interrupt priorities. The LM3S102 microcontroller supports 14 interrupts with eight priority levels.
2.2.6.2
SysTick Calibration Value Registers The SysTick Calibration Value register is not implemented.
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3
Memory Map
The memory map for the LM3S102 is provided in Table 3-1. In this manual, register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. See also Chapter 4, "Memory Map" in the ARM(R) CortexTM-M3 Technical Reference Manual.
Table 3-1. Memory Map (Sheet 1 of 2)
Start Memory 0x00000000 0x00002000 0x20000000 0x20000400 0x22000000 0x22010000 FiRM Peripherals 0x40000000 0x40001000 0x40004000 0x40005000 0x40006000 0x40007000 0x40008000 0x40009000 0x4000C000 0x4000D000 0x40010000 Peripherals 0x40020000 0x40020800 0x40021000 0x40024000 0x400207FF 0x40020FFF 0x40023FFF 0x40027FFF I2C Master I2C Slave Reserveda Reserveda page 274 page 288 0x40000FFF 0x40003FFF 0x40004FFF 0x40005FFF 0x40006FFF 0x40007FFF 0x40008FFF 0x4000BFFF 0x4000CFFF 0x4000FFFF 0x4001FFFF Watchdog timer Reserved for three additional watchdog timers (per FiRM specification)a GPIO Port A GPIO Port B GPIO Port C Reserved for additional GPIO port (per FiRM specification)a SSI Reserved for three additional SSIs (per FiRM specification)a UART0 Reserved for additional UART (per FiRM specification)a Reserved for future FiRM peripheralsa page 172 page 107 page 107 page 107 page 240 page 199 0x00001FFF 0x1FFFFFFF 0x200003FF 0x200FFFFF 0x2200FFFF 0x23FFFFFF On-chip flash Reserveda Bit-banded on-chip SRAM Reserveda Bit-band alias of 0x20000000 through 0x200003FF Reserveda page 90 End Description For details on registers, see ...
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Memory Map
Table 3-1. Memory Map (Sheet 2 of 2)
Start 0x40028000 0x4002C000 0x40030000 0x40031000 0x40032000 0x40038000 0x4003C000 0x4003D000 0x400FD000 0x400FE000 0x40100000 0x42000000 0x44000000 End 0x4002BFFF 0x4002FFFF 0x40030FFF 0x40031FFF 0x40037FFF 0x4003BFFF 0x4003CFFF 0x400FCFFF 0x400FDFFF 0x400FFFFF 0x41FFFFFF 0x43FFFFFF 0xDFFFFFFF Description Reserveda Reserveda Timer0 Timer1 Reserveda Reserveda Analog comparator Reserved
a
For details on registers, see ... page 149 page 149 page 299 page 90 page 55 -
Flash control System control Reserveda Bit-band alias of 0x40000000 through 0x400FFFFF Reserveda
Private Peripheral Bus 0xE0000000 0xE0001000 0xE0002000 0xE0003000 0xE000E000 0xE000F000 0xE0040000 0xE0041000 0xE0042000 0xE0100000 0xE0000FFF 0xE0001FFF 0xE0002FFF 0xE000DFFF 0xE000EFFF 0xE003FFFF 0xE0040FFF 0xE0041FFF 0xE00FFFFF 0xFFFFFFFF Instrumentation Trace Macrocell (ITM) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserveda Nested Vectored Interrupt Controller (NVIC) Reserveda Trace Port Interface Unit (TPIU) Reserveda Reserveda Reserved for vendor peripheralsa ARM(R) CortexTM-M3 Technical Reference Manual
a. All reserved space returns a bus fault when read or written.
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4
Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 4-1 lists all the exceptions. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 14 interrupts (listed in Table 4-2). Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. All the interrupt registers are described in Chapter 8, "Nested Vectored Interrupt Controller" in the ARM(R) CortexTM-M3 Technical Reference Manual. Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and a Hard Fault. Note that 0 is the default priority for all the settable priorities. If you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority. See Chapter 5, "Exceptions" and Chapter 8, "Nested Vectored Interrupt Controller" in the ARM(R) CortexTM-M3 Technical Reference Manual for more information on exceptions and interrupts. Table 4-1. Exception Types
Exception Type Position 0 1 Prioritya Description Stack top is loaded from first entry of vector table on reset. Invoked on power up and warm reset. On first instruction, drops to lowest priority (and then is called the base level of activation). This is asynchronous. Cannot be stopped or preempted by any exception but reset. This is asynchronous. An NMI is only producible by software, using the NVIC Interrupt Control State register. Hard Fault 3
Reset
-3 (highest)
Non-Maskable Interrupt (NMI)
2
-2
-1
All classes of Fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. This is synchronous. MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed.
Memory Management
4
settable
Bus Fault
5
settable
Pre-fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault.
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Interrupts
Table 4-1. Exception Types (Continued)
Exception Type Usage Fault Position 6 Prioritya settable Description Usage fault, such as undefined instruction executed or illegal state transition attempt. This is synchronous. Reserved. System service call with SVC instruction. This is synchronous. Debug monitor (when not halting). This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Reserved. Pendable request for system service. This is asynchronous and only pended by software. System tick timer has fired. This is asynchronous. Asserted from outside the ARM Cortex-M3 core and fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 lists the interrupts on the LM3S102 controller.
SVCall Debug Monitor
7-10 11 12
settable settable
PendSV SysTick Interrupts
13 14 15 16 and above
settable settable settable
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Interrupt (Bit in Interrupt Registers) 0 1 2 3-4 5 6 7 8 9-17 18 19 20 21 Description GPIO Port A GPIO Port B GPIO Port C Reserved UART0 Reserved SSI I2C Reserved Watchdog timer Timer0a Timer0b Timer1a
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Table 4-2. Interrupts (Continued)
Interrupt (Bit in Interrupt Registers) 22 23-24 25 26-27 28 29 30-31 Description Timer1b Reserved Analog Comparator 0 Reserved System Control Flash Control Reserved
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JTAG Interface
5
JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. The multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for the ARM, LMI, and unimplemented JTAG instructions. The JTAG module has the following features: IEEE 1149.1-1990 compatible Test Access Port (TAP) controller Four-bit Instruction Register (IR) chain for storing JTAG instructions IEEE standard instructions: - BYPASS instruction - IDCODE instruction - SAMPLE/PRELOAD instruction - EXTEST instruction - INTEST instruction ARM additional instructions: - APACC instruction - DPACC instruction - ABORT instruction Integrated ARM Serial Wire Debug (SWD) See the ARM(R) CortexTM-M3 Technical Reference Manual for more information on the ARM JTAG controller.
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5.1
Block Diagram
Figure 5-1. JTAG Module Block Diagram
TRST TCK TMS TDI
TAP Controller
Instruction Register (IR)
BYPASS Data Register Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register
TDO
Cortex-M3 Debug Port
5.2
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 on page 44 for a list of implemented instructions). See "JTAG and Boundary Scan" on page 324 for JTAG timing diagrams.
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JTAG Interface
5.2.1
JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1. Detailed information on each pin follows. Table 5-1. JTAG Port Pins Reset State
Pin Name TRST TCK TMS TDI TDO Data Direction Input Input Input Input Output Internal Pull-Up Enabled Enabled Enabled Enabled Enabled Internal Pull-Down Disabled Disabled Disabled Disabled Disabled Drive Strength N/A N/A N/A N/A 2-mA driver Drive Value N/A N/A N/A N/A High-Z
5.2.1.1
Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2
Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source.
5.2.1.3
Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2 on page 42.
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By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 5.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 5.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states.
5.2.2
JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 42. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1.
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JTAG Interface
Figure 5-2. Test Access Port State Machine
Test Logic 1 0 Run Test Idle 0 1 Select DR Scan 0 1 Capture DR 0 Shift DR 1 Exit 1 DR 0 Pause DR 1 0 Exit 2 DR 1 Update DR 1 0 0 0 0 1 1 1 Select IR Scan 0 Capture IR 0 Shift IR 1 Exit 1 IR 0 Pause IR 1 Exit 2 IR 1 Update IR 1 0 0 0 1 1
5.2.3
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller's CAPTURE states and allows this information to be shifted out of TDO during the TAP controller's SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller's UPDATE states. Each of the shift registers is discussed in detail in "Shift Registers" on page 42.
5.2.4
Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes requires clarification.
5.2.4.1
GPIO Functionality When the controller is reset with either a POR or RST, the JTAG port pins default to their JTAG configurations. The default configuration includes enabling the pull-up resistors (setting GPIOPUR
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to 1 for PB7 and PC[3:0]) and enabling the alternate hardware function (setting GPIOAFSEL to 1 for PB7 and PC[3:0]) on the JTAG pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0]in the GPIOAFSEL register. If the user does not require the JTAG port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution - If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger does not have enough time to connect and halt the controller before the JTAG pin functionality switches. This locks the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality using an external trigger. 5.2.4.2 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR, Select IR, and Test-Logic-Reset states. Stepping through the JTAG TAP Instruction Register (IR) load sequences of the TAP state machine twice without shifting in a new instruction enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM(R) CortexTM-M3 Technical Reference Manual and the ARM(R) CoreSight Technical Reference Manual. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occuring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface.
5.3
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
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JTAG Interface
5.4
Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2. A detailed explanation of each instruction, along with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
IR[3:0] 0000 0001 0010 1000 1010 1011 1110 1111 All Others Instruction EXTEST INTEST SAMPLE / PRELOAD ABORT DPACC APACC IDCODE BYPASS Reserved Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. Shifts data into the ARM Debug Port Abort Register. Shifts data into and out of the ARM DP Access Register. Shifts data into and out of the ARM AC Access Register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. Connects TDI to TDO through a single Shift Register chain. Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO.
5.4.1.1
EXTEST Instruction The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows tests to be developed that drive known values out of the controller, which can be used to verify connectivity.
5.4.1.2
INTEST Instruction The INTEST instruction does not have an associated Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/ PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows
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tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 5.4.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see "Boundary Scan Data Register" on page 46 for more information. 5.4.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the "ABORT Data Register" on page 47 for more information. 5.4.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see "DPACC Data Register" on page 47 for more information. 5.4.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see "APACC Data Register" on page 47 for more information. 5.4.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see "IDCODE Data Register" on page 46 for more information.
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JTAG Interface
5.4.1.8
BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see "BYPASS Data Register" on page 46 for more information.
5.4.2
Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections.
5.4.2.1
IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-3. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x1BA00477. This value indicates an ARM Cortex-M3, Version 1 processor. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
31 TDI 28 27 Part Number 12 11 Manufacturer ID 10 1 TDO
Version
5.4.2.2
BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-4. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. Figure 5-4. BYPASS Register Format
0 TDI 0 TDO
5.4.2.3
Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 5-5. Each GPIO pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These
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signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because the reset pin is always an input, only the input signal is included in the Data Register chain. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 5-5. Boundary Scan Register Format
TDI I N O U T GPIO PB6 O E
...
I N
O U T GPIO m
O E
I N RST
I N
O U T GPIO m+1
O E
...
I N
O U T GPIO n
O TDO E
For detailed information on the order of the input, output, and output enable bits for each of the GPIO ports, please refer to the Stellaris Family Boundary Scan Description Language (BSDL) files, downloadable from www.luminarymicro.com. 5.4.2.4 APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM(R) CortexTM-M3 Technical Reference Manual. 5.4.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM(R) CortexTM-M3 Technical Reference Manual. 5.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM(R) CortexTM-M3 Technical Reference Manual.
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System Control
6
System Control
System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting.
6.1
Functional Description
The System Control module provides the following capabilities: Device identification, see page 48 Local control, such as reset (see page 48), power (see page 51) and clock control (see page 51) System control (Run, Sleep, and Deep-Sleep modes), see page 53
6.1.1
Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, Flash size, and other features. See the DID0, DID1 and DC0-DC4 registers starting on page 56.
6.1.2
Reset Control
This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence.
6.1.2.1
Reset Sources The controller has six sources of reset: 1. External reset input pin (RST) assertion, see page 48. 2. Power-on reset (POR), see page 49. 3. Internal brown-out (BOR) detector, see page 49. 4. Software-initiated reset (with the software reset registers), see page 50. 5. A watchdog timer reset condition violation, see page 50. 6. Internal low drop-out (LDO) regulator output, see page 51. After a reset, the Reset Cause (RESC) register (see page 73) is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the RESC register are cleared. Note: The main oscillator is used for external resets and power-on resets; the internal oscillator is used during the internal process by internal reset and clock verification circuitry.
6.1.2.2
RST Pin Assertion The external reset pin (RST) resets the controller. This resets the core and all the peripherals except the JTAG TAP controller (see "JTAG Interface" on page 38). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted and then de-asserted. 2. After RST is de-assserted, the main crystal oscillator must be allowed to settle and there is an internal main oscillator counter that takes from 15-30 ms to account for this. During this time, internal reset to the rest of the controller is held active.
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3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The external reset timing is shown in Figure 18-9 on page 327. 6.1.2.3 Power-On Reset (POR) The Power-On Reset (POR) circuitry detects a rise in power-supply voltage and generates an on-chip reset pulse. To use the on-chip circuitry, the RST input needs a pull-up resistor (1K to 10K ). The device must be operating within the specified operating parameters at the point when the on-chip power-on reset pulse is complete. The specified operating parameters include supply voltage, frequency, temperature, and so on. If the operating conditions are not met at the point of POR end, the Stellaris controller does not operate correctly. In this case, the reset must be extended using external circuitry. The RST input may be used with the circuit as shown in Figure 6-1. Figure 6-1. External Circuitry to Extend Reset
Stellaris D1 R1 RST C1 R2
The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from the RST input. The diode discharges C1 rapidly when the power supply is turned off. The Power-On Reset sequence is as follows: 1. The controller waits for the later of external reset (RST) or internal POR to go inactive. 2. After the resets are inactive, the main crystal oscillator must be allowed to settle and there is an internal main oscillator counter that takes from 15-30 ms to account for this. During this time, internal reset to the rest of the controller is held active. 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing is shown in Figure 18-10 on page 327. 6.1.2.4 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if VDD drops below VBTH. The circuit is provided to guard against improper operation of logic and peripherals that operate off VDD and not the LDO voltage. If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. The BOR circuit has a digital filter that protects against noise-related detection. This feature may be optionally enabled.
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System Control
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register (see page 64). The BORIOR bit in the PBORCTL register must be set for a brown-out to trigger a reset. The brown-out reset sequence is as follows: 1. When VDD drops below VBTH, an internal BOR condition is set. 2. If the BORWT bit in the PBORCTL register is set, the BOR condition is resampled sometime later (specified by BORTIM) to determine if the original condition was caused by noise. If the BOR condition is not met the second time, then no action is taken. 3. If the BOR condition exists, an internal reset is asserted. 4. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. 5. The internal BOR signal is released after 500 s to prevent another BOR condition from being set before software has a chance to investigate the original cause. The internal Brown-Out Reset timing is shown in Figure 18-11 on page 327. 6.1.2.5 Software Reset Each peripheral can be reset by software. There are three registers that control this function (see the SRCRn registers, starting on page 66). If the bit position corresponding to a peripheral is set, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see "System Control" on page 53). Writing a bit lane with a value of 1 initiates a reset of the corresponding unit. Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software also. Setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset in initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 18-12 on page 327. 6.1.2.6 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register (see page 173), and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted.
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3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The watchdog reset timing is shown in Figure 18-13 on page 328. 6.1.2.7 Low Drop-Out A reset can be made when the internal low drop-out (LDO) regulator output goes unregulated. This is initially disabled and may be enabled by software. LDO is controlled with the LDO Power Control (LDOPCTL) register (see page 65). The LDO reset sequence is as follows: 1. LDO goes unregulated and the LDOARST bit in the LDOARST register is set. 2. An internal reset is asserted. 3. The internal reset is released and the controller fetches and loads the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The LDO reset timing is shown in Figure 18-14 on page 328.
6.1.3
Power Control
The LDO regulator permits the adjustment of the on-chip output voltage (VOUT). The output may be adjusted in 50 mV increments between the range of 2.25 V through 2.75 V. The adjustment is made through the VADJ field of the LDO Power Control (LDOPCTL) register (see page 65).
6.1.4
6.1.4.1
Clock Control
System control determines the clocking and control of clocks in this part. Fundamental Clock Sources There are two fundamental clock sources for use in the device: The main oscillator, driven from either an external crystal or a single-ended source. As a crystal, the main oscillator source is specified to run from 1-8 MHz. However, when the crystal is being used as the PLL source, it must be from 3.579545-8.192 MHz to meet PLL requirements. As a single-ended source, the range is from DC to the specified speed of the device. The internal oscillator, which is an on-chip free running clock. The internal oscillator is specified to run at 12 MHz 50%. It can be used to clock the system, but the tolerance of frequency range must be met. The internal system clock may be driven by either of the above two reference sources as well as the internal PLL, provided that the PLL input is connected to a clock source that meets its AC requirements. Nearly all of the control for the clocks is provided by the Run-Mode Clock Configuration (RCC) register (see page 74). Figure 6-2 shows the logic for the main clock tree. The peripheral blocks are driven by the System Clock signal and can be programmatically enabled/disabled.
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System Control
Figure 6-2. Main Clock Tree
USESYSDIVa OSC1 OSC2 Main Osc 1-8 MHz SYSDIVa Internal Osc 15 MHz PLL /4 OSCSRC
a
System Clock
(200 MHz output )
OEN
a a
BYPASS
a
XTAL
PWRDNa
a. These are bit fields within the Run-Mode Clock Configuration(RCC) register.
6.1.4.2
PLL Frequency Configuration The user does not have direct control over the PLL frequency, but is required to match the external crystal used to an internal PLL-Crystal table. This table is used to create the best fit for PLL parameters to the crystal chosen. Not all crystals result in the PLL operating at exactly 200 MHz, though the frequency is within 1%. The result of the lookup is kept in the XTAL to PLL Translation (PLLCTL) register (see page 78). Table 6-4 on page 77 describes the available crystal choices and default programming of the PLLCTL register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register (see page 74). Any time the XTAL field changes, a read of the internal table is performed to get the correct value. Table 6-4 on page 77 describes the available crystal choices and default programming values.
6.1.4.3
PLL Modes The PLL has two modes of operation: Normal and Power-Down Normal: The PLL multiplies the input clock reference and drives the output. Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC register fields as shown in Table 6-4 on page 77.
6.1.4.4
PLL Operation If the PLL configuration is changed, the PLL output is not stable for a period of time (PLL TREADY=0.5 ms) and during this time, the PLL is not usable as a clock reference. The PLL is changed by one of the following: Change to the XTAL value in the RCC register (see page 74)--writes of the same value do not cause a relock. Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 s at a 8.192-MHz external oscillator clock). Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the
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two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC register is switched to use the PLL. 6.1.4.5 Clock Verification Timers There are three identical clock verification circuits that can be enabled though software. The circuit checks the faster clock by a slower clock using timers: The main oscillator checks the PLL. The main oscillator checks the internal oscillator. The internal oscillator divided by 64 checks the main oscillator. If the verification timer function is enabled and a failure is detected, the main clock tree is immediately switched to a working clock and an interrupt is generated to the controller. Software can then determine the course of action to take. The actual failure indication and clock switching does not clear without a write to the CLKVCLR register, an external reset, or a POR reset. The clock verification timers are controlled by the PLLVER, IOSCVER, and MOSCVER bits in the RCC register (see page 74).
6.1.5
System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. The DC1, DC2 and DC4 registers act as a write mask for the RCGCn, SCGCn, and DCGCn registers. In Run mode, the controller is actively executing code. In Sleep mode, the clocking of the device is unchanged but the controller no longer executes code (and is no longer clocked). In Deep-Sleep mode, the clocking of the device may change (depending on the Run mode clock configuration) and the controller no longer executes code (and is no longer clocked). An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Each mode is described in more detail in this section.
6.1.5.1
Run Mode Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL.
6.1.5.2
Sleep Mode In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the SCGCn register when Auto Clock Gating is enabled (see RCC register on page 74) or the RCGCn register when the Auto Clock Gating is disabled. The System Clock has the same source and frequency as that during Run mode.
6.1.5.3
Deep-Sleep Mode The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when Auto Clock Gating is enabled (see RCC register) or the RCGCn register when the Auto Clock Gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled (see page 83). When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides the SYSDIV field of the active RCC register to be /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that were stopped during the Deep-Sleep duration.
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System Control
6.2
Initialization and Configuration
The PLL is configured using direct register writes to the Run-Mode Clock Configuration (RCC) register. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a "raw" clock source (using the main oscillator or internal oscillator) and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN and OE bits in RCC. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN and OE bits powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. If the PLL doesn't lock, the configuration is invalid. 5. Enable use of the PLL by clearing the BYPASS bit in RCC. Important: If the BYPASS bit is cleared before the PLL locks, it is possible to render the device unusable.
6.3
Register Map
Table 6-1 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400FE000.
Table 6-1. System Control Register Map (Sheet 1 of 2)
Offset Name Reset Type Description See page
Device Identification and Capabilities 0x000 0x004 0x008 0x010 0x014 0x018 0x01C DID0 DID1 DC0 DC1 DC2 DC3 DC4 0x00070003 0x00000009 0x01031011 0x830001C0 0x00000007 RO RO RO RO RO RO RO Device identification 0 Device identification 1 Device capabilities 0 Device capabilities 1 Device capabilities 2 Device Capabilities 3 Device Capabilities 4 56 57 59 60 61 62 63
Local Control 0x030 0x034 0x040 PBORCTL LDOPCTL SRCR0 0x00007FFD 0x00000000 0x00000000 R/W R/W R/W Power-On and Brown-Out Reset Control LDO Power Control Software Reset Control 0 64 65 66
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Table 6-1. System Control Register Map (Sheet 2 of 2)
Offset 0x044 0x048 0x050 0x054 0x058 0x05C 0x060 0x064 Name SRCR1 SRCR2 RIS IMC MISC RESC RCC PLLCFG Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x07803AC0 Type R/W R/W RO R/W R/W1C R/W R/W RO Description Software Reset Control 1 Software Reset Control 2 Raw Interrupt Status Interrupt Mask Control Masked Interrupt Status and Clear Reset Cause Run-Mode Clock Configuration XTAL to PLL translation See page 67 68 69 70 72 73 74 78
System Control 0x100 0x104 0x108 0x110 0x114 0x118 0x120 0x124 0x128 0X144 0x150 0x160 RCGC0 RCGC1 RCGC2 SCGC0 SCGC1 SCGC2 DCGC0 DCGC1 DCGC2 DSLPCLKCFG CLKVCLR LDOARST 0x00000001 0x00000000 0x00000000 0x00000001 0x00000000 0x00000000 0x00000001 0x00000000 0x00000000 0x07800000 0x00000000 0x00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Run-Mode Clock Gating Control 0 Run-Mode Clock Gating Control 1 Run-Mode Clock Gating Control 2 Sleep-Mode Clock Gating Control 0 Sleep-Mode Clock Gating Control 1 Sleep-Mode Clock Gating Control 2 Deep-Sleep-Mode Clock Gating Control 0 Deep-Sleep-Mode Clock Gating Control 1 Deep-Sleep-Mode Clock Gating Control 2 Deep-Sleep Clock Configuration Clock verification clear Allow unregulated LDO to reset the part 79 80 82 79 80 82 79 80 82 83 84 85
6.4
Register Descriptions
The remainder of this section lists and describes the System Control registers, in numerical order by address offset.
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System Control
Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device.
Device Identification 0 (DID0)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14
VER
RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7
reserved
RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
MAJOR
Type Reset
RO RO RO RO RO RO RO RO RO RO RO RO -
MINOR
RO RO RO RO -
Bit/Field 31
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This field defines the version of the DID0 register format: 0=Register version for the Stellaris microcontrollers
30:28
VER
RO
0
27:16
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. This field specifies the major revision number of the device. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: 0: Revision A (initial device) 1: Revision B (first revision) and so on.
15:8
MAJOR
RO
-
7:0
MINOR
RO
-
This field specifies the minor revision number of the device. This field is numeric and is encoded as follows: 0: No changes. Major revision was most recent update. 1: One interconnect change made since last major revision update. 2: Two interconnect changes made since last major revision update. and so on.
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Register 2: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, and package type.
Device Identification 1 (DID1)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VER
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10
FAM
RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5
PARTNO
RO 0 4 RO 0 3 RO 0 2 RO 1 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO -
TEMP
RO RO RO 0
PKG
RO 0
RoHS
RO 1 RO -
QUAL
RO -
Bit/Field 31:28
Name VER
Type RO
Reset 0x0
Description This field defines the version of the DID1 register format: 0=Register version for the Stellaris microcontrollers
27:24
FAM
RO
0x0
Family This field provides the family identification of the device within the Luminary Micro product portfolio. The 0x0 value indicates the Stellaris family of microcontrollers.
23:16
PARTNO
RO
0x02
Part Number This field provides the part number of the device within the family. The 0x02 value indicates the LM3S102 microcontroller.
15:8
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. Temperature Range This field specifies the temperature rating of the device. This field is encoded as follows: TEMP 000 001 010-111 Description Commercial temperature range (0C to 70C) Industrial temperature range (-40C to 85C) Reserved
7:5
TEMP
RO
see table
4:3
PKG
RO
0x0
This field specifies the package type. A value of 0 indicates a 28-pin SOIC package. RoHS-Compliance A 1 in this bit specifies the device is RoHS-compliant.
2
RoHS
RO
1
October 6, 2006 Preliminary
57
System Control
Bit/Field 1:0
Name QUAL
Type RO
Reset see table
Description This field specifies the qualification status of the device. This field is encoded as follows: QUAL 00 01 10 11 Description Engineering Sample (unqualified) Pilot Production (unqualified) Fully Qualified Reserved
58 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 3: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features.
Device Capabilities Register 0 (DC0)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAMSZ
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 1 2 RO 1 1 RO 1 0
FLSHSZ
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1
Bit/Field 31:16
Name SRAMSZ
Type RO
Reset 0x0007
Description Indicates the size of the on-chip SRAM. A value of 0x0007 indicates 2 KB of SRAM. Indicates the size of the on-chip flash memory. A value of 0x03 indicates 8 KB of Flash.
15:0
FLSHSZ
RO
0x0003
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59
System Control
Register 4: Device Capabilities 1 (DC1), offset 0x010 This register is predefined by the part and can be used to verify features.
Device Capabilities 1 (DC1)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
MINSYSDIV
Type Reset
RO 1 RO 0 RO 0 RO 1 RO 0
reserved
RO 0 RO 0 RO 0
MPU
RO 0
reserved
RO 0 RO 0
PLL
RO 1
WDT
RO 1
SWO
RO 1
SWD
RO 1
JTAG
RO 1
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. The reset value is hardware-dependent. A value of 0x09 specifies a 20-MHz CPU clock with a PLL divider of 10. See the RCC register (page 74) for how to change the system clock divisor using the SYSDIV bit. Reserved bits return an indeterminate value, and should never be changed. This bit indicates whether the Memory Protection Unit (MPU) in the Cortex-M3 is available. A 0 in this bit indicates the MPU is not available; a 1 indicates the MPU is available. See the ARM(R) CortexTM-M3 Technical Reference Manual for details on the MPU.
15:12
MINSYSDIV
RO
0x09
11:8
reserved
RO
0
7
MPU
RO
0
6:5
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of an implemented PLL in the device. A 1 in this bit indicates a watchdog timer on the device. A 1 in this bit indicates the presence of the ARM Serial Wire Output (SWO) trace port capabilities. A 1 in this bit indicates the presence of the ARM Serial Wire Debug (SWD) capabilities. A 1 in this bit indicates the presence of a JTAG port.
4
PLL WDTa SWOa SWDa JTAGa
RO
1
3 2
RO RO
1 1
1
RO
1
0
RO
1
a. These bits mask the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 113), Sleep-Mode Clock Gating Control 0 (SCGC0) register (see page 113), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that are not noted are passed as 0.
60 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 5: Device Capabilities 2 (DC2), offset 0x014 This register is predefined by the part and can be used to verify features.
Device Capabilities 2 (DC2)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9
COMP0
RO 1 8 RO 0 7 RO 0 6
reserved
RO 0 5 RO 0 4 RO 0 3 RO 0 2
GPTM1 GPTM0
RO 1 1 RO 1 0
reserved
Type Reset
RO 0 RO 0 RO 0
I2C
RO 1 RO 0 RO 0 RO 0
reserved
RO 0 RO 0 RO 0 RO 0
SSI
RO 1 RO 0
reserved
RO 0 RO 0
UART0
RO 1
Bit/Field 31:25
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of analog comparator 0. Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of General-Purpose Timer module 1. A 1 in this bit indicates the presence of General-Purpose Timer module 0. Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of the I2C module. Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of the SSI module. Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of the UART0 module.
24
COMP0
RO
1
23:18
reserved
RO
0
17
GPTM1
RO
1
16
GPTM0
RO
1
15:13
reserved
RO
0
12 11:5
I2C reserved
RO RO
1 0
4 3:1
SSI reserved
RO RO
1 0
0
UART0
RO
1
October 6, 2006 Preliminary
61
System Control
Register 6: Device Capabilities 3 (DC3), offset 0x018 This register is predefined by the part and can be used to verify features.
Device Capabilities 3 (DC3)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
32KHz
Type Reset
RO 1 15 RO 0 14 RO 0 13
reserved
RO 0 12 RO 0 11 RO 0 10
CCP1
RO 1 9
CCP0
RO 1 8 RO 0 7 RO 0 6 RO 0 5
reserved
RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
C0o
RO 1
C0+
RO 1
C0RO 1 RO 0 RO 0
reserved
RO 0 RO 0 RO 0 RO 0
Bit/Field 31
Name 32KHz
Type RO
Reset 1
Description A 1 in this bit indicates the presence of a 32.768-KHz input pin. Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of the Capture/ Compare/PWM pin 1. A 1 in this bit indicates the presence of the Capture/ Compare/PWM pin 0. Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of the C0o pin. A 1 in this bit indicates the presence of the C0+ pin. A 1 in this bit indicates the presence of the C0- pin. Reserved bits return an indeterminate value, and should never be changed.
30:26
reserved
RO
0
25
CCP1
RO
1
24
CCP0
RO
1
23:9
reserved
RO
0
8 7 6 5:0
C0o C0+ C0reserved
RO RO RO RO
1 1 1 0
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October 6, 2006
LM3S102 Data Sheet
Register 7: Device Capabilities 4 (DC4), offset 0x01C This register is predefined by the part and can be used to verify features.
Device Capabilities 4 (DC4)
Offset 0x01C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PORTC PORTB PORTA
RO 1 RO 1 RO 1
Bit/Field 31:3
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. A 1 in this bit indicates the presence of GPIO Port C. A 1 in this bit indicates the presence of GPIO Port B. A 1 in this bit indicates the presence of GPIO Port A.
2 1 0
PORTC PORTB PORTA
RO RO RO
1 1 1
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63
System Control
Register 8: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset.
Power-On and Brown-Out Reset Control (PBORCTL)
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
BORTIM
Type Reset
R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1
BORIOR BORWT
R/W 0 R/W 1
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This field specifies the number of internal oscillator clocks delayed before the BOR output is resampled if the BORWT bit is set. The width of this field is derived by the tBOR width of 500 s and the internal oscillator (IOSC) frequency of 15 MHz 50%. At +50%, the counter value has to exceed 10,000.
15:2
BORTIM
R/W
0x1FFF
1
BORIOR
R/W
0
BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled.
0
BORWT
R/W
1
BOR Wait and Check for Noise This bit specifies the response to a brown-out signal assertion. If BORWT is set to 1, the controller waits BORTIM IOSC periods before resampling the BOR output, and if asserted, it signals a BOR condition interrupt or reset. If the BOR resample is deasserted, the cause of the initial assertion was likely noise and the interrupt or reset is suppressed. If BORWT is 0, BOR assertions do not resample the output and any condition is reported immediately if enabled.
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October 6, 2006
LM3S102 Data Sheet
Register 9: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Offset 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
VADJ
R/W 0 R/W 0 R/W 0
Bit/Field 31:6
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This field sets the on-chip output voltage. The programming values for the VADJ field are provided in Table 6-2.
5:0
VADJ
R/W
0x0
Table 6-2. VADJ to VOUT
VADJ Value 0x1B 0x1C 0x1D 0x1E VOUT (V) 2.75 2.70 2.65 2.60 VADJ Value 0x1F 0x00 0x01 0x02 VOUT (V) 2.55 2.50 2.45 2.40 VADJ Value 0x03 0x04 0x05 0x06-0x3F VOUT (V) 2.35 2.30 2.25 Reserved
October 6, 2006 Preliminary
65
System Control
Register 10: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register (see page 60).
Software Reset Control 0 (SRCR0)
Offset 0x040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 R/W 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
WDT
R/W 0 RO 0
reserved
RO 0 RO 0
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Reset control for the Watchdog unit. Reserved bits return an indeterminate value, and should never be changed.
3 2:0
WDT reserved
R/W RO
0 0
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October 6, 2006
LM3S102 Data Sheet
Register 11: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register (see page 61).
Software Reset Control 1 (SRCR1)
Offset 0x044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9
COMP0
R/W 0 8 RO 0 7 RO 0 6
reserved
RO 0 5 RO 0 4 RO 0 3 RO 0 2
GPTM1 GPTM0
R/W 0 1 R/W 0 0
reserved
Type Reset
RO 0 RO 0 RO 0
I2C
R/W 0 RO 0 RO 0 RO 0
reserved
RO 0 RO 0 RO 0 RO 0
SSI
R/W 0 RO 0
reserved
RO 0 RO 0
UART0
R/W 0
Bit/Field 31:25
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Reset control for analog comparator 0. Reserved bits return an indeterminate value, and should never be changed. Reserved bits return an indeterminate value, and should never be changed. Reset control for General-Purpose Timer module 1. Reset control for General-Purpose Timer module 0. Reserved bits return an indeterminate value, and should never be changed. Reset control for the I2C units. Reserved bits return an indeterminate value, and should never be changed. Reset control for the SSI units. Reserved bits return an indeterminate value, and should never be changed. Reset control for the UART0 module.
24 23:19
COMP0 reserved
R/W RO
0 0
18
reserved
RO
0
17 16 15:13
GPTM1 GPTM0 reserved
R/W R/W RO
0 0 0
12 11:5
I2C reserved
R/W RO
0 0
4 3:1
SSI reserved
R/W RO
0 0
0
UART0
R/W
0
October 6, 2006 Preliminary
67
System Control
Register 12: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register (see page 63).
Software Reset Control (SRCR2)
Offset 0x048
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PORTC PORTB PORTA
R/W 0 R/W 0 R/W 0
Bit/Field 31:3
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Reset control for GPIO Port C. Reset control for GPIO Port B. Reset control for GPIO Port A.
2 1 0
PORTC PORTB PORTA
R/W R/W R/W
0 0 0
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October 6, 2006
LM3S102 Data Sheet
Register 13: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Offset 0x050
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PLLLRIS CLRIS
RO 0 RO 0
IOFRIS MOFRIS LDORIS BORRIS PLLFRIS
RO 0 RO 0 RO 0 RO 0 RO 0
Bit/Field 31:7
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts.
6
PLLLRIS
RO
0
5
CLRIS
RO
0
Current Limit Raw Interrupt Status This bit is set if the LDO's CLE output asserts.
4
IOFRIS
RO
0
Internal Oscillator Fault Raw Interrupt Status This bit is set if an internal oscillator fault is detected.
3
MOFRIS
RO
0
Main Oscillator Fault Raw Interrupt Status This bit is set if a main oscillator fault is detected.
2
LDORIS
RO
0
LDO Power Unregulated Raw Interrupt Status This bit is set if a LDO voltage is unregulated.
1
BORRIS
RO
0
Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition was detected. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared.
0
PLLFRIS
RO
0
PLL Fault Raw Interrupt Status This bit is set if a PLL fault is detected (stops oscillating).
October 6, 2006 Preliminary
69
System Control
Register 14: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Offset 0x054
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PLLLIM
R/W 0
CLIM
R/W 0
IOFIM
R/W 0
MOFIM LDOIM BORIM PLLFIM
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:7
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. PLL Lock Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated.
6
PLLLIM
R/W
0
5
CLIM
R/W
0
Current Limit Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if CLRIS is set; otherwise, an interrupt is not generated.
4
IOFIM
R/W
0
Internal Oscillator Fault Interrupt Mask This bit specifies whether an internal oscillator fault detection is promoted to a controller interrupt. If set, an interrupt is generated if IOFRIS is set; otherwise, an interrupt is not generated.
3
MOFIM
R/W
0
Main Oscillator Fault Interrupt Mask This bit specifies whether a main oscillator fault detection is promoted to a controller interrupt. If set, an interrupt is generated if MOFRIS is set; otherwise, an interrupt is not generated.
2
LDOIM
R/W
0
LDO Power Unregulated Interrupt Mask This bit specifies whether an LDO unregulated power situation is promoted to a controller interrupt. If set, an interrupt is generated if LDORIS is set; otherwise, an interrupt is not generated.
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October 6, 2006
LM3S102 Data Sheet
Bit/Field 1
Name BORIM
Type R/W
Reset 0
Description Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated.
0
PLLFIM
R/W
0
PLL Fault Interrupt Mask This bit specifies whether a PLL fault detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLFRIS is set; otherwise, an interrupt is not generated.
October 6, 2006 Preliminary
71
System Control
Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058 Central location for system control result of RIS AND IMC to generate an interrupt to the controller. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 69).
Masked Interrupt Status and Clear (MISC)
Offset 0x058
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PLLLMIS CLMIS IOFMIS MOFMIS LDOMIS BORMIS PLLFMIS
R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0
Bit/Field 31:7
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit.
6
PLLLMIS
R/W1C
0
5
CLMIS
R/W1C
0
Current Limit Masked Interrupt Status This bit is set if the LDO's CLE output asserts. The interrupt is cleared by writing a 1 to this bit.
4
IOFMIS
R/W1C
0
Internal Oscillator Fault Masked Interrupt Status This bit is set if an internal oscillator fault is detected. The interrupt is cleared by writing a 1 to this bit.
3
MOFMIS
R/W1C
0
Main Oscillator Fault Masked Interrupt Status This bit is set if a main oscillator fault is detected. The interrupt is cleared by writing a 1 to this bit.
2
LDOMIS
R/W1C
0
LDO Power Unregulated Masked Interrupt Status This bit is set if LDO power is unregulated. The interrupt is cleared by writing a 1 to this bit.
1
BORMIS
R/W1C
0
Brown-Out Reset Masked Interrupt Status This bit is the masked interrupt status for any brown-out conditions. If set, a brown-out condition was detected. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. The interrupt is cleared by writing a 1 to this bit.
0
PLLFMIS
R/W1C
0
PLL Fault Masked Interrupt Status This bit is set if a PLL fault is detected (stops oscillating). The interrupt is cleared by writing a 1 to this bit.
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October 6, 2006
LM3S102 Data Sheet
Register 16: Reset Cause (RESC), offset 0x05C This field specifies the cause of the reset event to software. The reset value is determined by the cause of the reset. When an external reset is the cause (EXT is set), all other reset bits are cleared. However, if the reset is due to any other cause, the remaining bits are sticky, allowing software to see all causes.
Reset Cause (RESC)
Offset 0x05C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
LDO
R/W -
SW
R/W -
WDT
R/W -
BOR
R/W -
POR
R/W -
EXT
R/W -
Bit/Field 31:6
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. When set to 1, LDO power OK lost is the cause of the reset event. When set to 1, a software reset is the cause of the reset event. When set to 1, a watchdog reset is the cause of the reset event. When set to 1, a brown-out reset is the cause of the reset event. When set to 1, a power-on reset is the cause of the reset event. When set to 1, an external reset (RST assertion) is the cause of the reset event.
5
LDO
R/W
-
4
SW
R/W
-
3
WDT
R/W
-
2
BOR
R/W
-
1
POR
R/W
-
0
EXT
R/W
-
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73
System Control
Register 17: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Offset 0x060
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12
ACG
R/W 0 11 R/W 1 10 R/W 1 9
SYSDIV
R/W 1 8 R/W 1 7
USESYSDIV R/W 0 6 RO 0 5 RO 0 4
reserved
RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0
PWRDN
R/W 1
OEN
R/W 1
BYPASS
R/W 1
PLLVER
R/W 0 R/W 1 R/W 0
XTAL
R/W 1 R/W 1 R/W 0
OSCSRC
R/W 0
IOSCVER MOSCVER IOSCDIS MOSCDIS
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:28
Name Reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers (see page 79) and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers (see page 79) if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers (see page 79) are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused.
27
ACG
R/W
0
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October 6, 2006
LM3S102 Data Sheet
Bit/Field 26:23
Name SYSDIV
Type R/W
Reset 0xF
Description System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output (200 MHz). Binary Value 00001000 1001 1010 1011 1100 1101 1110 1111 Divisor (BYPASS=1) reserved /10 /11 /12 /13 /14 /15 /16 Frequency (BYPASS=0) reserved 20 MHz 18.18 MHz 16.67 MHz 15.38 MHz 14.29 MHz 13.33 MHz 12.5 MHz (default)
When reading the Run-Mode Clock Configuration (RCC) register (see page 74), the SYSDIV value is MINSYSDIV if a lower divider was requested and the PLL is being used. This lower value is allowed to divide a non-PLL source. 22 USESYSDIV R/W 0 Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. Reserved bits return an indeterminate value, and should never be changed. PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. See Table 6-4 on page 77 for PLL mode control. 12 OEN R/W 1 PLL Output Enable This bit specifies whether the PLL output driver is enabled. If cleared, the driver transmits the PLL clock to the output. Otherwise, the PLL clock does not oscillate outside the PLL module. Note: Both PWRDN and OEN must be cleared to run the PLL.
21:14
reserved
RO
0
13
PWRDN
R/W
1
11
BYPASS
R/W
1
PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider.
October 6, 2006 Preliminary
75
System Control
Bit/Field 10
Name PLLVER
Type R/W
Reset 0
Description PLL Verification This bit controls the PLL verification timer function. If set, the verification timer is enabled and an interrupt is generated if the PLL becomes inoperative. Otherwise, the verification timer is not enabled.
9:6
XTAL
R/W
0xB
This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided in Table 6-4 on page 77.
Oscillator-Related Bits 5:4 OSCSRC R/W 0x0 Picks among the four input sources for the OSC. The values are: Value 00 01 10 11 3 IOSCVER R/W 0 Input Source Main oscillator (default) Internal oscillator Internal oscillator / 4 (this is necessary if used as input to PLL) reserved
This bit controls the internal oscillator verification timer function. If set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. Otherwise, the verification timer is not enabled. This bit controls the main oscillator verification timer function. If set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. Otherwise, the verification timer is not enabled. Internal Oscillator Disable 0: Internal oscillator is enabled. 1: Internal oscillator is disabled.
2
MOSCVER
R/W
0
1
IOSCDIS
R/W
0
0
MOSCDIS
R/W
0
Main Oscillator Disable 0: Main oscillator is enabled. 1: Main oscillator is disabled.
Table 6-3. PLL Mode Control
PWRDN 1 0 OEN X 0 Mode Power down Normal
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LM3S102 Data Sheet
Table 6-4. Default Crystal Field Values and PLL Programming
Crystal Number (XTAL Binary Value) 0000-0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Crystal Frequency (MHz) reserved 3.579545 MHz 3.6864 MHz 4 MHz 4.096 MHz 4.9152 MHz 5 MHz 5.12 MHz 6 MHz (reset value) 6.144 MHz 7.3728 MHz 8 MHz 8.192 MHz
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System Control
Register 18: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 74).
XTAL to PLL Translation (PLLCFG)
Offset 0x064
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
OD
Type Reset
RO RO RO RO RO RO -
F
RO RO RO RO RO RO RO -
R
RO RO RO -
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This field specifies the value supplied to the PLL's OD input. This field specifies the value supplied to the PLL's F input. This field specifies the value supplied to the PLL's R input.
15:14 13:5 4:0
OD F R
RO RO RO
-
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LM3S102 Data Sheet
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110 Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120 These registers control the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register (see page 74) specifies that the system uses sleep modes.
Run-Mode, Sleep-Mode and Deep-Sleep-Mode Clock Gating Control 0 (RCGC0, SCGC0, and DCGC0)
Offset 0x100, 0x110, 0x120
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
WDT
R/W 0
SWO
R/W 0
SWD
R/W 0
JTAG
R/W 1
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a This bit controls the clock gating for the SWO module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a This bit controls the clock gating for the SWD module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a This bit controls the clock gating for the JTAG module. The reset state for this bit is 1. At reset, the unit receives a clock and functions. Setting this bit to 0 leaves the unit unclocked and disabled.a
3
WDT
R/W
0
2
SWO
R/W
0
1
SWD
R/W
0
0
JTAG
R/W
1
a.
If the unit is unclocked, reads or writes to the unit will generate a bus fault.
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System Control
Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114 Register 24: Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124 These registers control the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register (see page 74) specifies that the system uses sleep modes.
Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 1 (RCGC1, SCGC1, and DCGC1)
Offset 0x104, 0x114, and 0x124
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9
COMP0
R/W 0 8 RO 0 7 RO 0 6
reserved
RO 0 5 RO 0 4 RO 0 3 RO 0 2
GPTM1 GPTM0
R/W 0 1 R./W 0 0
reserved
Type Reset
RO 0 RO 0 RO 0
I2C
R/W 0 RO 0 RO 0 RO 0
reserved
RO 0 RO 0 RO 0 RO 0
SSI
R/W 0 RO 0
reserved
RO 0 RO 0
UART0
R/W 0
Bit/Field 31:25
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit controls the clock gating for the Comparator 0 module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a Reserved bits return an indeterminate value, and should never be changed. This bit controls the clock gating for the General Purpose Timer 1 module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a This bit controls the clock gating for the General Purpose Timer 0 module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a Reserved bits return an indeterminate value, and should never be changed.
24
COMP0
R/W
0
23:18
reserved
RO
0
17
GPTM1
R/W
0
16
GPTM0
R/W
0
15:13
reserved
RO
0
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LM3S102 Data Sheet
Bit/Field 12
Name I2C
Type R/W
Reset 0
Description This bit controls the clock gating for the I2C module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a Reserved bits return an indeterminate value, and should never be changed. This bit controls the clock gating for the SSI module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a Reserved bits return an indeterminate value, and should never be changed. This bit controls the clock gating for the UART0 module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a
11:5
reserved
RO
0
4
SSI
R/W
0
3:1
reserved
RO
0
0
UART0
R/W
0
a.
If the unit is unclocked, reads or writes to the unit will generate a bus fault.
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System Control
Register 25: Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 Register 26: Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118 Register 27: Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128 These registers control the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register (see page 74) specifies that the system uses sleep modes.
Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 2 (RCGC2, SCGC2, and DCGC2)
Offset 0x108, 0x118, and 0x128
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PORTC PORTB PORTA
R/W 0 R/W 0 R/W 0
Bit/Field 31:3
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit controls the clock gating for the GPIO Port C module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a This bit controls the clock gating for the GPIO Port B module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a This bit controls the clock gating for the GPIO Port A module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.a
2
PORTC
R/W
0
1
PORTB
R/W
0
0
PORTA
R/W
0
a.
If the unit is unclocked, reads or writes to the unit will generate a bus fault.
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LM3S102 Data Sheet
Register 28: Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register is used to automatically switch from the main oscillator to the internal oscillator when entering Deep-Sleep mode. The system clock source is the main oscillator by default. When this register is set, the internal oscillator is powered up and the main oscillator is powered down. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode.
Deep-Sleep Clock Configuration (DSLPCLKCFG)
Offset 0x144
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
IOSC
R/W 0
Bit/Field 31:1
Name Reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This field allows an override of the main oscillator when Deep-Sleep mode is running. When set, this field forces the internal oscillator to be the clock source during Deep-Sleep mode. Otherwise, the main oscillator remains as the default system clock source.
0
IOSC
R/W
0
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System Control
Register 29: Clock Verification Clear (CLKVCLR), offset 0x150 This register is provided as a means of clearing the clock verification circuits by software. Since the clock verification circuits force a known good clock to control the process, the controller is allowed the opportunity to solve the problem and clear the verification fault. This register clears all clock verification faults. To clear a clock verification fault, the VERCLR bit must be set and then cleared by software. This bit is not self-clearing.
Clock Verification Clear (CLKVCLR)
Offset 0x150
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
VERCLR
R/W 0
Bit/Field 31:1
Name Reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Clear clock verification faults.
0
VERCLR
R/W
0
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LM3S102 Data Sheet
Register 30: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 This register is provided as a means of allowing the LDO to reset the part if the voltage goes unregulated. Use this register to choose whether to automatically reset the part if the LDO goes unregulated, based on the design tolerance for LDO fluctuation.
Allow Unregulated LDO to Reset the Part (LDOARST)
Offset 0x160
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
LDOARST
R/W 0
Bit/Field 31:1
Name Reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Set to 1 to allow unregulated LDO output to reset the part.
0
LDOARST
R/W
0
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Internal Memory
7
Internal Memory
The LM3S102 microcontroller comes with 2 KB of bit-banded SRAM and 8 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis.
7.1
Block Diagram
Figure 7-1. Flash Block Diagram
Flash Timing USECRL
Flash Control ICode Cortex-M3 DCode FMA FMD FMC System Bus FCRIS FCIM FCMISC Bridge APB Flash Array
Flash Protection FMPRE SRAM Array FMPPE
7.2
7.2.1
Functional Description
This section describes the functionality of both memories.
SRAM Memory
The internal SRAM of the Stellaris devices is located at address 0x20000000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation.
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LM3S102 Data Sheet
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x20001000 is to be modified, the bit-band alias is calculated as:
0x22000000 + (0x1000 * 32) + (3 * 4) = 0x2202000C
With the alias address calculated, an instruction performing a read/write to address 0x2202000C allows direct access to only bit 3 of the byte at address 0x20001000. For details about bit-banding, please refer to Chapter 4, "Memory Map" in the ARM(R) CortexTM-M3 Technical Reference Manual.
7.2.2
Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger.
7.2.2.1
Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register (see page 92). On reset, USECRL is loaded with a value that configures the flash timing so that it works with the selected crystal value. If software changes the system operating frequency, the new operating frequency must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 must be written to the USECRL register.
7.2.2.2
Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in two 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPE and FMPRE registers (see page 91). Flash Memory Protection Program Enable (FMPPE): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. Flash Memory Protection Read Enable (FMPRE): If set, the block may be executed or read by software or debuggers. If cleared, the block may only be executed. The contents of the memory block are prohibited from being accessed as data and traversing the DCode bus.
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Internal Memory
The policies may be combined as shown in Table 7-1. Table 7-1. Flash Protection Policy Combinations
FMPPE 0 1 0 FMPRE 0 0 1 Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. The block may be written, erased or executed, but not read. This combination is unlikely to be used. Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. No protection. The block may be written, erased, executed or read.
1
1
An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers of poorly behaving software during the development and debug phases. An access that attempts to read an RE-protected block is prohibited. Such accesses return data filled with all 0s. A controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. 7.2.2.3 Flash Memory Programming Writing the flash memory requires that the code be executed out of SRAM to avoid corrupting or interrupting the bus timing. Flash pages can be erased on a page basis (1 KB in size), or by performing a mass erase of the entire flash. All erase and program operations are performed using the Flash Memory Address (FMA), Flash Memory Data (FMD) and Flash Memory Control (FMC) registers. See section 7.3 for examples.
7.3
Initialization and Configuration
This section shows examples for using the flash controller to perform various operations on the contents of the flash memory.
7.3.1
Changing Flash Protection Bits
As discussed in Section 7.2.2.2, changes to the protection bits must be committed before they take effect. The sequence to change and commit a bit in software is as follows: 1. The Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection Program Enable (FMPPE) registers are written, changing the intended bit(s). The action of these changes can be tested by software while in this state. 2. The Flash Memory Address (FMA) register (see page 93) bit 0 is set to 1 if the FMPPE register is to be committed; otherwise, a 0 commits the FMPRE register. 3. The Flash Memory Control (FMC) register (see page 95) is written with the COMT bit set. This initiates a write sequence and commits the changes.
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LM3S102 Data Sheet
7.3.2
Flash Programming
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD and FMC. The flash is programmed using the following sequence: 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA4420001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. To perform an erase of a 1-KB page: 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA4420002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. To perform a mass erase of the flash: 1. Write the flash write key and the MERASE bit (a value of 0xA4420004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared.
7.4
Register Map
Table 7-2 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address, relative to the Flash control base address of 0x400FD000, except for FMPRE and FMPPE, which are relative to the System Control base address of 0x400FE000.
Table 7-2. Flash Register Map
Offset 0x130a 0x134
a
Name FMPRE FMPPE USECRL FMA FMD FMC FCRIS FCIM FCMISC
Reset 0x0F 0x0F 0x13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
Type R/W0 R/W0 R/W R/W R/W R/W RO R/W R/W1C
Description Flash memory read protect Flash memory program protect USec reload Flash memory address Flash memory data Flash memory control Flash controller raw interrupt status Flash controller interrupt mask Flash controller masked interrupt status and clear
See page 91 91 92 93 94 95 97 98 99
0X140a 0x000 0x004 0x008 0x00C 0x010 0x014
a. Relative to System Control base address of 0x400FE000.
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Internal Memory
7.5
Register Descriptions
The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset.
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LM3S102 Data Sheet
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130 Register 2: Flash Memory Protection Program Enable (FMPPE), offset 0x134 Note: Offset is relative to System Control base address of 0x400FE000 These registers store the read-only (FMPRE) and execute-only (FMPPE) protection bits for each 2 KB flash block. This register is loaded during the power-on reset sequence. The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see "Flash Memory Protection" on page 87.
Flash Memory Protection Read Enable and Program Enable (FMPRE and FMPPE)
Offset 0x130 and 0x134
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
Block3
R/W0 1
Block2
R/W0 1
Block1
R/W0 1
Block0
R/W0 1
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Enable 2-KB flash blocks to be written or erased (FMPPE register), or executed or read (FMPRE register). The policies may be combined as shown in Table 7-1 on page 88.
3:0
Block3Block0
R/W0
0x0F
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Internal Memory
Register 3: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400FE000 This register is provided as a means of creating a 1 s tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation.
Usec Reload (USECRL)
Offset 0x140
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
USEC
R/W 1 R/W 0 R/W 0 R/W 1 R/W 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. MHz -1 of the controller clock when the flash is being erased or programmed. USEC should be set to 0x13 (19 MHz) whenever the flash is being erased or programmed.
7:0
USEC
R/W
0x13
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LM3S102 Data Sheet
Register 4: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable.
Flash Memory Address (FMA)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
OFFSET
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:13
Name reserved
Type RO
Reset 0x0
Description Reserved bits return an indeterminate value, and should never be changed. Address offset in flash where operation is performed.
12:0
OFFSET
R/W
0x0
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Internal Memory
Register 5: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
Type Reset
R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0
DATA
Type Reset
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:0
Name DATA
Type R/W
Reset 0x0
Description Data value for write operation.
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LM3S102 Data Sheet
Register 6: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 93). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 94) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable.
Flash Memory Control (FMC)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRKEY
Type Reset
WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 WO 0 2 WO 0 1 WO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
COMT MERASE ERASE WRITE
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:16
Name WRKEY
Type WO
Reset 0x0
Description This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. Reserved bits return an indeterminate value, and should never be changed. Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 s.
15:4
reserved
RO
0
3
COMT
R/W
0
2
MERASE
R/W
0
Mass erase flash memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms.
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Bit/Field 1
Name ERASE
Type R/W
Reset 0
Description Erase a page of flash memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms.
0
WRITE
R/W
0
Write a word into flash memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 s.
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LM3S102 Data Sheet
Register 7: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PRIS
RO 0
ARIS
RO 0
Bit/Field 31:2
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Programming Raw Interrupt Status This bit indicates the current state of the programming cycle. If set, the programming cycle completed; if cleared, the programming cycle has not completed. Programming cycles are either write or erase actions generated through the Flash Memory Control (FMC) register bits (see page 95).
1
PRIS
RO
0
0
ARIS
RO
0
Access Raw Interrupt Status This bit indicates if the flash was improperly accessed. If set, the program tried to access the flash counter to the policy as set in the Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection Program Enable (FMPPE) registers (see page 91). Otherwise, no access has tried to improperly access the flash.
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Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PMASK AMASK
R/W 0 R/W 0
Bit/Field 31:2
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the controller. If set, a programming-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller.
1
PMASK
R/W
0
0
AMASK
R/W
0
Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the controller. If set, an access-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller.
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LM3S102 Data Sheet
Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PMISC
R/W1C 0
AMISC
R/W1C 0
Bit/Field 31:2
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Programming Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. This bit is cleared by writing a 1. The PRIS bit in the FCRIS register (see page 97) is also cleared when the PMISC bit is cleared.
1
PMISC
R/W1C
0
0
AMISC
R/W1C
0
Access Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared.
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General-Purpose Input/Outputs (GPIOs)
8
General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of three physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, and Port C). The GPIO module is FiRM-compliant and supports up to 18 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: Programmable control for GPIO interrupts: - Interrupt generation masking - Edge-triggered on rising, falling, or both - Level-sensitive on High or Low values 5-V-tolerant input/outputs Bit masking in both read and write operations through address lines Programmable control for GPIO pad configuration: - Weak pull-up or pull-down resistors - 2-mA, 4-mA, and 8-mA pad drive - Slew rate control for the 8-mA drive - Open drain enables - Digital input enables
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8.1
Block Diagram
Figure 8-1. GPIO Module Block Diagram
PA0 GPIO Port A PA1 PA2 PA3 PA4 PA5
U0Rx U0Tx SSIClk SSIFss SSIRx SSITx
UART0
SSI
PB0 PB1 GPIO Port B PB2 PB3 PB4 PB5 PB6 PB7
CCP1 CCP0 32KHz I2CSCL I2CSDA C0C0o C0+ IC
2
Timer 0 Timer 1
Analog Comparator
PC1 PC2 PC3
GPIO Port C
PC0
TCK/SWCLK TMS/SWDIO
TRST JTAG
TDI TDO/SWO
8.2
Functional Description
Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception of the five JTAG pins (PB7 and PC[3:0]. The JTAG pins default to their JTAG functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an external reset (RST) puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-2). The LM3S102 microcontroller contains three ports and thus three of these physical GPIO blocks.
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General-Purpose Input/Outputs (GPIOs)
Figure 8-2. GPIO Port Block Diagram
Function Selection GPIOAFSEL Alternate Input Alternate Output Alternate Output Enable GPIO Input GPIO Output GPIO Output Enable
M U X D E M U X M U X
Pad Input
Pad Output
I/O Data GPIODATA GPIODIR
I/O Pad
Package I/O Pin
Pad Output Enable
Interrupt Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR
I/O Pad Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN
Interrupt
Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3
8.2.1
Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 108) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 8-3, where u is data unchanged by the write.
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Figure 8-3. GPIODATA Write Example
ADDR[9:2] 0x098 0xEB GPIODATA 9 0 1 u 7 8 0 1 u 6 7 1 1 1 5 6 0 0 u 4 5 0 1 u 3 4 1 0 0 2 3 1 1 1 1 2 0 1 u 0 1 0 0 0
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-4. Figure 8-4. GPIODATA Read Example
ADDR[9:2] 0x0C4 GPIODATA Returned Value 9 0 1 0 7 8 0 0 0 6 7 1 1 1 5 6 1 1 1 4 5 0 1 0 3 4 0 1 0 2 3 0 1 0 1 2 1 0 0 0 1 0 0 0
8.2.2
Data Direction
The GPIO Direction (GPIODIR) register (see page 109) is used to configure each individual pin as an input or output.
8.2.3
Interrupt Operation
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: GPIO Interrupt Sense (GPIOIS) register (see page 110) GPIO Interrupt Both Edges (GPIOIBE) register (see page 111) GPIO Interrupt Event (GPIOIEV) register (see page 112) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 113). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see pages 114 and 115). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
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General-Purpose Input/Outputs (GPIOs)
Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 116). When programming interrupts, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled.
8.2.4
Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 117), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins.
8.2.5
Pad Configuration
The pad configuration registers allow for GPIO pad configuration by software based on the application requirements. The pad configuration registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
8.2.6
Identification
The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers.
8.3
Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting PORTA, PORTB, and PORTC in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose input mode (GPIODIR and GPIOAFSEL both set to 0). Table 8-1 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-2 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 8-1. GPIO Pad Configuration Examples
Register Bit Valuea GPIOAFSEL GPIODR2R GPIODR4R GPIODR8R X ? X ? ? X ? GPIOODR GPIODEN GPIOPUR GPIOPDR GPIOSLR X ? X ? ? X ? GPIODIR 0 1 0 1 X X X
Configuration
Digital Input (GPIO) Digital Output (GPIO) Open Drain Input (GPIO) Open Drain Output (GPIO) Open Drain Input/Output (I2C) Digital Input (Timer CCP) Digital Output (Timer PWM)
0 0 0 0 1 1 1
0 0 1 1 1 0 0
1 1 1 1 1 1 1
? ? X X X ? ?
? ? X X X ? ?
X ? X ? ? X ?
X ? X ? ? X ?
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Table 8-1. GPIO Pad Configuration Examples (Continued)
Register Bit Valuea GPIOAFSEL GPIODR2R GPIODR4R GPIODR8R ? ? X ? GPIOODR GPIODEN GPIOPUR GPIOPDR GPIOSLR ? ? X ? 0 X X X 0 105 Preliminary GPIODIR X X 0 X
Configuration
Digital Input/Output (SSI) Digital Input/Output (UART) Analog Input (Comparator) Digital Output (Comparator)
1 1 0 1
0 0 0 0
1 1 0 1
? ? 0 ?
? ? 0 ?
? ? X ?
? ? X ?
a. X=Ignored (don't care bit) ?=Can be either 0 or 1, depending on the configuration
Table 8-2. GPIO Interrupt Configuration Example
Desired Interrupt Event Trigger 0=edge 1=level 0=single edge 1=both edges 0=Low level, or negative edge 1=High level, or positive edge 0=masked 1=not masked Pin 2 Bit Valuea 7 X X 6 X X 5 X X 4 X X 3 X X 2 0 0 1 X X
Register
GPIOIS GPIOIBE GPIOIEV
X
X
X
X
X
1
X
GPIOIM
0
0
0
0
0
1
0
a. X=Ignored (don't care bit)
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General-Purpose Input/Outputs (GPIOs)
8.4
Register Map
Table 8-2 lists the GPIO registers. The offset listed is a hexadecimal increment to the register's address, relative to that GPIO port's base address: GPIO Port A: 0x40004000 GPIO Port B: 0x40005000 GPIO Port C: 0x40006000 Important: The GPIO registers in this chapter are duplicated in each GPIO block, however, depending on the block, all eight bits may not be connected to a GPIO pad (see Figure 8-1 on page 101). In those cases, writing to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data.
Table 8-3. GPIO Register Map
Offset 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0xFD0 0xFD4 0xFD8 Name GPIODATA GPIODIR GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR GPIOAFSEL GPIODR2R GPIODR4R GPIODR8R GPIOODR GPIOPUR GPIOPDR GPIOSLR GPIODEN GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 see notea 0x000000FF 0x00000000 0x00000000 0x00000000 0x000000FF 0x00000000 0x00000000 0x000000FF 0x00000000 0x00000000 0x00000000 Type R/W R/W R/W R/W R/W R/W RO RO W1C R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO Description Data Data direction Interrupt sense Interrupt both edges Interrupt event Interrupt mask enable Raw interrupt status Masked interrupt status Interrupt clear Alternate function select 2-mA drive select 4-mA drive select 8-mA drive select Open drain select Pull-up select Pull-down select Slew rate control select Digital input enable Peripheral identification 4 Peripheral identification 5 Peripheral identification 6 See page 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
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LM3S102 Data Sheet
Table 8-3. GPIO Register Map (Continued)
Offset 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name GPIOPeriphID7 GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Reset 0x00000000 0x00000061 0x00000000 0x00000018 0x00000001 0x0000000D 0x000000F0 0x00000005 0x000000B1 Type RO RO RO RO RO RO RO RO RO Description Peripheral identification 7 Peripheral identification 0 Peripheral identification 1 Peripheral identification 2 Peripheral identification 3 GPIO PrimeCell identification 0 GPIO PrimeCell identification 1 GPIO PrimeCell identification 2 GPIO PrimeCell identification 3 See page 129 130 131 132 133 134 135 136 137
a. The default reset value for the GPIOAFSEL register is 0x00000000 for all GPIO pins, with the exception of the five JTAG pins (PB7 and PC[3:0]. These five pins default to JTAG functionality. Because of this, the default reset value of GPIOAFSEL for GPIO Port B is 0x00000080 while the default reset value of GPIOAFSEL for Port C is 0x0000000F.
8.5
Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address offset.
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General-Purpose Input/Outputs (GPIOs)
Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 109). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset.
GPIO Data (GPIODATA)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
DATA
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See "Data Register Operation" on page 102 for examples of reads and writes.
7:0
DATA
R/W
0
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LM3S102 Data Sheet
Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
Offset 0x400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
DIR
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Data Direction 0: Pins are inputs. 1: Pins are outputs.
7:0
DIR
R/W
0x00
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General-Purpose Input/Outputs (GPIOs)
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
Offset 0x404
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
IS
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Sense 0: Edge on corresponding pin is detected (edge-sensitive). 1: Level on corresponding pin is detected (level-sensitive).
7:0
IS
R/W
0x00
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LM3S102 Data Sheet
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 110) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 112). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
Offset 0x408
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
IBE
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Both Edges 0: Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 142). 1: Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV.
7:0
IBE
R/W
0x00
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General-Purpose Input/Outputs (GPIOs)
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 110). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
Offset 0x40C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
IEV
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Event 0: Falling edge or Low levels on corresponding pins trigger interrupts. 1: Rising edge or High levels on corresponding pins trigger interrupts.
7:0
IEV
R/W
0x00
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LM3S102 Data Sheet
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
Offset 0x410
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
IME
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Mask Enable 0: Corresponding pin interrupt is masked. 1: Corresponding pin interrupt is not masked.
7:0
IME
R/W
0x00
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General-Purpose Input/Outputs (GPIOs)
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 113). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
Offset 0x414
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
RIS
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Raw Status Reflect the status of interrupt trigger condition detection on pins (raw, prior to masking). 0: Corresponding pin interrupt requirements not met. 1: Corresponding pin interrupt has met requirements.
7:0
RIS
RO
0x00
114 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
Offset 0x418
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
MIS
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. 0: Corresponding GPIO line interrupt not active. 1: Corresponding GPIO line asserting interrupt.
7:0
MIS
RO
0x00
October 6, 2006 Preliminary
115
General-Purpose Input/Outputs (GPIOs)
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
Offset 0x41C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 W1C 0 W1C 0 W1C 0 W1C 0
IC
W1C 0 W1C 0 W1C 0 W1C 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Interrupt Clear 0: Corresponding interrupt is unaffected. 1: Corresponding interrupt is cleared.
7:0
IC
W1C
0x00
116 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. Caution - All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an external reset (RST) puts both groups of pins back to their default state. If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger.
GPIO Alternate Function Select (GPIOAFSEL)
Offset 0x420
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W R/W R/W -
AFSEL
R/W R/W R/W R/W R/W -
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Alternate Function Select 0: Software control of corresponding GPIO line (GPIO mode). 1: Hardware control of corresponding GPIO line (alternate hardware function). Note: The default reset value for the GPIOAFSEL register is 0x00 for all GPIO pins, with the exception of the five JTAG pins (PB7 and PC[3:0]). These five pins default to JTAG functionality. Because of this, the default reset value of GPIOAFSEL for GPIO Port B is 0x80 while the default reset value of GPIOAFSEL for Port C is 0x0F.
7:0
AFSEL
R/W
see note
October 6, 2006 Preliminary
117
General-Purpose Input/Outputs (GPIOs)
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
Offset 0x500
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1
DRV2
R/W 1 R/W 1 R/W 1 R/W 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write.
7:0
DRV2
R/W
0xFF
118 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
Offset 0x504
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
DRV4
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write.
7:0
DRV4
R/W
0x00
October 6, 2006 Preliminary
119
General-Purpose Input/Outputs (GPIOs)
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
Offset 0x508
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
DRV8
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write.
7:0
DRV8
R/W
0x00
120 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 125). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output when set to 1. When using the I2C module, the GPIO Alternate Function Select (GPIOAFSEL) register bit for PB2 and PB3 should be set to 1 (see examples in "Initialization and Configuration" on page 104).
GPIO Open Drain Select (GPIOODR)
Offset 0x50C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
ODE
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Output Pad Open Drain Enable 0: Open drain configuration is disabled. 1: Open drain configuration is enabled.
7:0
ODE
R/W
0x00
October 6, 2006 Preliminary
121
General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 123).
GPIO Pull-Up Select (GPIOPUR)
Offset 0x510
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1
PUE
R/W 1 R/W 1 R/W 1 R/W 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write.
7:0
PUE
R/W
0xFF
122 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 122).
GPIO Pull-Down Select (GPIOPDR)
Offset 0x514
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
PDE
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write.
7:0
PDE
R/W
0x00
October 6, 2006 Preliminary
123
General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 120).
GPIO Slew Rate Control Select (GPIOSLR)
Offset 0x518
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
SRL
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Slew Rate Limit Enable (8-mA drive only) 0: Slew rate control disabled. 1: Slew rate control enabled.
7:0
SRL
R/W
0
124 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 18: GPIO Digital Input Enable (GPIODEN), offset 0x51C The GPIODEN register is the digital input enable register. By default, all GPIO signals are configured as digital inputs at reset. The only time that a pin should not be configured as a digital input is when the GPIO pin is configured to be one of the analog input signals for the analog comparator.
GPIO Digital Input Enable (GPIODEN)
Offset 0x51C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1
DEN
R/W 1 R/W 1 R/W 1 R/W 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Digital-Input Enable 0: Digital input disabled 1: Digital input enabled
7:0
DEN
R/W
0xFF
October 6, 2006 Preliminary
125
General-Purpose Input/Outputs (GPIOs)
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
Offset 0xFD0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID4
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[7:0]
7:0
PID4
RO
0x00
126 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
Offset 0xFD4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID5
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[15:8]
7:0
PID5
RO
0x00
October 6, 2006 Preliminary
127
General-Purpose Input/Outputs (GPIOs)
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
Offset 0xFD8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID6
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[23:16]
7:0
PID6
RO
0x00
128 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
Offset 0xFDC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID7
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[31:24]
7:0
PID7
RO
0x00
October 6, 2006 Preliminary
129
General-Purpose Input/Outputs (GPIOs)
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
Offset 0xFE0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0
PID0
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral.
7:0
PID0
RO
0x61
130 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 24: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
Offset 0xFE4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID1
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral.
7:0
PID1
RO
0x00
October 6, 2006 Preliminary
131
General-Purpose Input/Outputs (GPIOs)
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
Offset 0xFE8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1
PID2
RO 1 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral.
7:0
PID2
RO
0x18
132 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
Offset 0xFEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID3
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral.
7:0
PID3
RO
0x01
October 6, 2006 Preliminary
133
General-Purpose Input/Outputs (GPIOs)
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system.
GPIO Primecell Identification 0 (GPIOPCellID0)
Offset 0xFF0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
CID0
RO 1 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system.
7:0
CID0
RO
0x0D
134 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system.
GPIO Primecell Identification 1 (GPIOPCellID1)
Offset 0xFF4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1
CID1
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system.
7:0
CID1
RO
0xF0
October 6, 2006 Preliminary
135
General-Purpose Input/Outputs (GPIOs)
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system.
GPIO Primecell Identification 2 (GPIOPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
CID2
RO 0 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system.
7:0
CID2
RO
0x05
136 Preliminary
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LM3S102 Data Sheet
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system.
GPIO Primecell Identification 3 (GPIOPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1
CID3
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system.
7:0
CID3
RO
0xB1
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9
General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins. The LM3S102 controller General-Purpose Timer Module (GPTM) contains two GPTM blocks (Timer0 and Timer1). Each GPTM block provides two 16-bit timer/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). The following modes are supported: 32-bit Timer modes: - Programmable one-shot timer - Programmable periodic timer - Real-Time Clock using 32.768-KHz input clock - Software-controlled event stalling (excluding RTC mode) 16-bit Timer modes: - General-purpose timer function with an 8-bit prescaler - Programmable one-shot timer - Programmable periodic timer - Software-controlled event stalling 16-bit Input Capture modes: - Input edge count capture - Input edge time capture 16-bit PWM mode: - Simple PWM mode with software-programmable output inversion of the PWM signal
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9.1
Block Diagram
Figure 9-1. GPTM Module Block Diagram
0x0000 (Down Counter Modes )
TimerA Control GPTMTAPMR GPTMTAPR GPTMTAMATCHR Interrupt / Config TimerA Interrupt GPTMCFG GPTMCTL GPTMIMR TimerB Interrupt GPTMRIS GPTMMIS GPTMICR GPTMTBPMR GPTMTBPR GPTMTBMATCHR GPTMTBILR GPTMTBMR TB Comparator TimerB Control GPTMTBR En Clock / Edge Detect CCP1 RTC Divider GPTMTAILR GPTMTAMR GPTMAR En Clock / Edge Detect TA Comparator
32KHz
0x0000 (Down Counter Modes ) System Clock
9.2
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 150), the GPTM TimerA Mode (GPTMTAMR) register (see page 151), and the GPTM TimerB Mode (GPTMTBMR) register (see page 152). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes.
9.2.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 160) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 161). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 164) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 165).
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9.2.2
32-Bit Timer Operating Modes
Note: Both the odd- and even-numbered CCP pins are used for 16-bit mode. Only the even-numbered CCP pins are used for 32-bit mode.
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 160 GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 161 GPTM TimerA (GPTMTAR) register [15:0], see page 168 GPTM TimerB (GPTMTBR) register [15:0], see page 169 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0]. Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0]. 9.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 151), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 153), the timer begins counting down from its preloaded value. Once the 0x00000000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and output triggers when it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 157), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 159). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR) register (see page 155), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMISR) register (see page 158). The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x00000000 state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal is deasserted. 9.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x00000001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 162) by the controller.
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The 32KHZ pin is dedicated to the 32-bit RTC function, and the input clock is 32.768 KHz. When software writes the TAEN bit in GPTMCTL, the counter starts counting up from its preloaded value of 0x00000001. When the current count value matches the preloaded value in GPTMTAMATCHR, it rolls over to a value of 0x00000000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL.
9.2.3
16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 150). This section describes each of the GPTM 16-bit modes of operation. Timer A and Timer B have identical modes, so a single description is given using an n to reference both.
9.2.3.1
16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 20-MHz clock with Tc=20 ns (clock period).
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Table 9-1. 16-Bit Timer With Prescaler Configurations
Prescale 00000000 00000001 00000010 -----------11111100 11111110 11111111 a. TC is the clock period. #Clock (TC)a 1 2 3 -254 255 256 832.3073 835.584 838.8608 mS mS mS Max Time 3.2768 6.554 9.8302 Units mS mS mS
9.2.3.2
16-Bit Input Edge Count Mode In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 9-2 shows how input edge count mode works. In this case, the timer start value is set to GPTMnILR=0x000A and the match value is set to GPTMnMATCHR=0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register.
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Figure 9-2. 16-Bit Input Edge Count Mode Example
Timer reload on next cycle
Count
Ignored
Ignored
0x000A 0x0009 0x0008 0x0007 0x0006
Timer stops, flags asserted
Input Signal
9.2.3.3
16-Bit Input Edge Time Mode In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register. Figure 9-3 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR).
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Figure 9-3. 16-Bit Input Edge Time Mode Example
Count
0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z
Z
X
Y Time
Input Signal
9.2.3.4
16-Bit PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TNCMR bit to 0x0, and the TnMR field to 0x2. PWM mode can take advantage of the 8-bit prescaler by using the GPTM Timern Prescale Register (GPTMTnPR) and the GPTM Timern Prescale Match Register (GPTMTnPMR). This effectively extends the range of the timer to 24 bits. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 9-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML=0 (duty cycle would be 33% for the TnPWML=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A.
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Figure 9-4. 16-Bit PWM Mode Example
Count
0xC350 GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0x411A
Time
TnEN set TnPWML = 0
Output Signal
TnPWML = 1
9.3
Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the GPTM0 and GPTM1 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes.
9.3.1
32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR).
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In One-Shot mode, the timer stops counting after step 7. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.2
32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its 32KHz pin. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x00000000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
9.3.3
16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 8. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.4
16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3.
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4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat steps 4-9.
9.3.5
16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write.
9.3.6
16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TNCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
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7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register and the GPTM Timern Prescale Match (GPTMTnPMR) register. 8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write.
9.4
Register Map
Table 9-1 lists the GPTM registers. The offset listed is a hexadecimal increment to the register's address, relative to that timer's base address: Timer0: 0x40030000 Timer1: 0x40031000
Table 9-2. GPTM Register Map
Offset 0x000 0x004 0x008 0x00C 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 Name GPTMCFG GPTMTAMR GPTMTBMR GPTMCTL GPTMIMR GPTMRIS GPTMMIS GPTMICR GPTMTAILR GPTMTBILR GPTMTAMATCHR GPTMTBMATCHR GPTMTAPR GPTMTBPR GPTMTAPMR GPTMTBPMR Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000FFFFa 0xFFFFFFFF 0x0000FFFF 0x0000FFFF 0xFFFFFFFF 0x0000FFFF 0x00000000 0x00000000 0x00000000 0x00000000
a
Type R/W R/W R/W R/W R/W RO RO W1C R/W R/W R/W R/W R/W R/W R/W R/W
Description Configuration TimerA mode TimerB mode Control Interrupt mask Interrupt status Masked interrupt status Interrupt clear TimerA interval load TimerB interval load TimerA match TimerB match TimerA prescale TimerB prescale TimerA prescale match TimerB prescale match
See page 150 151 152 153 155 157 158 159 160 161 162 163 164 165 166 167
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Table 9-2. GPTM Register Map (Continued)
Offset 0x048 0x04C Name GPTMTAR GPTMTBR Reset 0x0000FFFFa 0xFFFFFFFF 0x0000FFFF Type RO RO Description TimerA TimerB See page 168 169
a. The default reset value for the GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers is 0x0000FFFF when in 16-bit mode and 0xFFFFFFFF when in 32-bit mode.
9.5
Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0
GPTMCFG
R/W 0 R/W 0
Bit/Field 31:3
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM Configuration 0x0: 32-bit timer configuration. 0x1: 32-bit real-time clock (RTC) counter configuration. 0x2: Reserved. 0x3: Reserved. 0x4-0x7: 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR.
2:0
GPTMCFG
R/W
0
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2.
GPTM TimerA Mode (GPTMTAMR)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
TAAMS TACMR
R/W 0 R/W 0 R/W 0
TAMR
R/W 0
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerA Alternate Mode Select 0: Capture mode is enabled. 1: PWM mode is enabled. Note: To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2.
3
TAAMS
R/W
0
2
TACMR
R/W
0
GPTM TimerA Capture Mode 0: Edge-Count mode. 1: Edge-Time mode.
1:0
TAMR
R/W
0
GPTM TimerA Mode 0x0: Reserved. 0x1: One-Shot Timer mode. 0x2: Periodic Timer mode. 0x3: Capture mode. The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored.
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General-Purpose Timers
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2.
GPTM TimerB Mode (GPTMTBMR)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
TBAMS TBCMR
R/W 0 R/W 0 R/W 0
TBMR
R/W 0
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Alternate Mode Select 0: Capture mode is enabled. 1: PWM mode is enabled. Note: To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2.
3
TBAMS
R/W
0
2
TBCMR
R/W
0
GPTM TimerB Capture Mode 0: Edge-Count mode. 1: Edge-Time mode.
1:0
TBMR
R/W
0
GPTM TimerB Mode 0x0: Reserved. 0x1: One-Shot Timer mode. 0x2: Periodic Timer mode. 0x3: Capture mode. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register's contents are ignored and GPTMTAMR is used.
152 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger.
GPTM Control (GPTMCTL)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
res
Type Reset
RO 0
TBPWML
R/W 0
TBOTE
R/W 0
res
RO 0
TBEVENT
R/W 0 R/W 0
TBSTALL
R/W 0
TBEN
R/W 0
res
RO 0
TAPWML TAOTE
R/W 0 R/W 0
RTCEN
R/W 0
TAEVENT
R/W 0 R/W 0
TASTALL
R/W 0
TAEN
R/W 0
Bit/Field 31:15
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB PWM Output Level 0: Output is unaffected. 1: Output is inverted.
14
TBPWML
R/W
0
13
TBOTE
R/W
0
GPTM TimerB Output Trigger Enable 0: The output TimerB trigger is disabled. 1: The output TimerB trigger is enabled.
12
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Event Mode 00: Positive edge. 01: Negative edge. 10: Reserved. 11: Both edges.
11:10
TBEVENT
R/W
0
9
TBSTALL
R/W
0
GPTM TimerB Stall Enable 0: TimerB stalling is disabled. 1: TimerB stalling is enabled.
8
TBEN
R/W
0
GPTM TimerB Enable 0: TimerB is disabled. 1: TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.
7
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed.
October 6, 2006 Preliminary
153
General-Purpose Timers
Bit/Field 6
Name TAPWML
Type R/W
Reset 0
Description GPTM TimerA PWM Output Level 0: Output is unaffected. 1: Output is inverted.
5
TAOTE
R/W
0
GPTM TimerA Output Trigger Enable 0: The output TimerA trigger is disabled. 1: The output TimerA trigger is enabled.
4
RTCEN
R/W
0
GPTM RTC Enable 0: RTC counting is disabled. 1: RTC counting is enabled.
3:2
TAEVENT
R/W
0
GPTM TimerA Event Mode 00: Positive edge. 01: Negative edge. 10: Reserved. 11: Both edges.
1
TASTALL
R/W
0
GPTM TimerA Stall Enable 0: TimerA stalling is disabled. 1: TimerA stalling is enabled.
0
TAEN
R/W
0
GPTM TimerA Enable 0: TimerA is disabled. 1: TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.
154 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0
CBEIM CBMIM TBTOIM
R/W 0 R/W 0 R/W 0 RO 0
reserved
RO 0 RO 0 RO 0
RTCIM
R/W 0
CAEIM CAMIM TATOIM
R/W 0 R/W 0 R/W 0
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM CaptureB Event Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled.
10
CBEIM
R/W
0
9
CBMIM
R/W
0
GPTM CaptureB Match Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled.
8
TBTOIM
R/W
0
GPTM TimerB Time-Out Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled.
7:4
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. GPTM RTC Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled.
3
RTCIM
R/W
0
2
CAEIM
R/W
0
GPTM CaptureA Event Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled.
October 6, 2006 Preliminary
155
General-Purpose Timers
Bit/Field 1
Name CAMIM
Type R/W
Reset 0
Description GPTM CaptureA Match Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled.
0
TATOIM
R/W
0
GPTM TimerA Time-Out Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled.
156 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Offset 0x01C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0
CBERIS
RO 0
CBMRIS TBTORIS
RO 0 RO 0 RO 0
reserved
RO 0 RO 0 RO 0
RTCRIS
RO 0
CAERIS
RO 0
CAMRIS TATORIS
RO 0 RO 0
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking.
10
CBERIS
RO
0
9
CBMRIS
RO
0
GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking.
8
TBTORIS
RO
0
GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking.
7:4
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking.
3
RTCRIS
RO
0
2
CAERIS
RO
0
GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking.
1
CAMRIS
RO
0
GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking.
0
TATORIS
RO
0
GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking.
October 6, 2006 Preliminary
157
General-Purpose Timers
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0
CBEMIS
RO 0
CBMMIS TBTOMIS
RO 0 RO 0 RO 0
reserved
RO 0 RO 0 RO 0
RTCMIS
RO 0
CAEMIS CAMMIS TATOMIS
RO 0 RO 0 RO 0
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking.
10
CBEMIS
RO
0
9
CBMMIS
RO
0
GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking.
8
TBTOMIS
RO
0
GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking.
7:4
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking.
3
RTCMIS
RO
0
2
CAEMIS
RO
0
GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking.
1
CAMMIS
RO
0
GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking.
0
TATOMIS
RO
0
GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking.
158 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Offset 0x024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 W1C 0
CBECINT CBMCINT TBTOCINT
W1C 0 W1C 0 W1C 0 RO 0 RO 0
reserved
RO 0 RO 0
RTCCINT CAECINT CAMCINTTATOCINT
W1C 0 W1C 0 W1C 0 W1C 0
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM CaptureB Event Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared.
10
CBECINT
W1C
0
9
CBMCINT
W1C
0
GPTM CaptureB Match Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared.
8
TBTOCINT
W1C
0
GPTM TimerB Time-Out Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared.
7:4
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. GPTM RTC Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared.
3
RTCCINT
W1C
0
2
CAECINT
W1C
0
GPTM CaptureA Event Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared.
1
CAMCINT
W1C
0
GPTM CaptureA Match Raw Interrupt This is the CaptureA match interrupt status after masking.
0
TATOCINT
W1C
0
GPTM TimerA Time-Out Raw Interrupt 0: The interrupt is unaffected. 1: The interrupt is cleared.
October 6, 2006 Preliminary
159
General-Purpose Timers
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Offset 0x028
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAILRH
Type Reset
R/W 1/0 15 R/W 1/0 14 R/W 1/0 13 R/W 1/0 12 R/W 1/0 11 R/W 1/0 10 R/W 1/0 9 R/W 1/0 8 R/W 1/0 7 R/W 1/0 6 R/W 1/0 5 R/W 1/0 4 R/W 1/0 3 R/W 1/0 2 R/W 1/0 1 R/W 1/0 0
TAILRL
Type Reset
R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
Bit/Field 31:16
Name TAILRH
Type R/W
Reset 0xFFFF (32-bit mode) 0x0000 (16-bit mode)
Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR.
15:0
TAILRL
R/W
0xFFFF
160 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Offset 0x02C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
TBILRL
Type Reset
R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR.
15:0
TBILRL
R/W
0xFFFF
October 6, 2006 Preliminary
161
General-Purpose Timers
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMRH
Type Reset
R/W 1/0 15 R/W 1/0 14 R/W 1/0 13 R/W 1/0 12 R/W 1/0 11 R/W 1/0 10 R/W 1/0 9 R/W 1/0 8 R/W 1/0 7 R/W 1/0 6 R/W 1/0 5 R/W 1/0 4 R/W 1/0 3 R/W 1/0 2 R/W 1/0 1 R/W 1/0 0
TAMRL
Type Reset
R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
Bit/Field 31:16
Name TAMRH
Type R/W
Reset 0xFFFF (32-bit mode) 0x0000 (16-bit mode)
Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value.
15:0
TAMRL
R/W
0xFFFF
162 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Offset 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
TBMRL
Type Reset
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value.
15:0
TBMRL
R/W
0xFFFF
October 6, 2006 Preliminary
163
General-Purpose Timers
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers.
GPTM TimerA Prescale (GPTMTAPR)
Offset 0x038
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
TAPSR
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-1 on page 142 for more details and an example.
7:0
TAPSR
R/W
0
164 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers.
GPTM TimerB Prescale (GPTMTBPR)
Offset 0x03C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
TBPSR
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-1 on page 142 for more details and an example.
7:0
TBPSR
R/W
0
October 6, 2006 Preliminary
165
General-Purpose Timers
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits.
GPTM TimerA Prescale Match (GPTMTAPMR)
Offset 0x040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
TAPSMR
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler.
7:0
TAPSMR
R/W
0
166 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits.
GPTM TimerB Prescale Match (GPTMTBPMR)
Offset 0x044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
TBPSMR
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler.
7:0
TBPSMR
R/W
0
October 6, 2006 Preliminary
167
General-Purpose Timers
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerA (GPTMTAR)
Offset 0x048
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TARH
Type Reset
RO 1/0 15 RO 1/0 14 RO 1/0 13 RO 1/0 12 RO 1/0 11 RO 1/0 10 RO 1/0 9 RO 1/0 8 RO 1/0 7 RO 1/0 6 RO 1/0 5 RO 1/0 4 RO 1/0 3 RO 1/0 2 RO 1/0 1 RO 1/0 0
TARL
Type Reset
RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
Bit/Field 31:16
Name TARH
Type RO
Reset 0xFFFF (32-bit mode) 0x0000 (16-bit mode)
Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero.
15:0
TARL
RO
0xFFFF
GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event.
168 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerB (GPTMTBR)
Offset 0x04C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
TBRL
Type Reset
RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event.
15:0
TBRL
RO
0xFFFF
October 6, 2006 Preliminary
169
Watchdog Timer
10
Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, a locking register, and user-enabled stalling. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered.
10.1
Block Diagram
WDT Module Block Diagram
Control / Clock / Interrupt Generation WDTCTL WDTICR WDTLOAD
Figure 10-1.
Interrupt
WDTRIS WDTMIS WDTLOCK
32-Bit Down Counter 0x00000000
System Clock
WDTTEST Comparator WDTVALUE
Identification Registers WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID3 WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDTPeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7
170 Preliminary
October 6, 2006
LM3S102 Data Sheet
10.2
Functional Description
The Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state.
10.3
Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACCE551.
10.4
Register Map
Table 10-1 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register's address, relative to the Watchdog Timer base address of 0x40000000.
Table 10-1. WDT Register Map
Offset 0x000 0x004 0x008 Name WDTLOAD WDTVALUE WDTCTL Reset 0xFFFFFFFF 0xFFFFFFFF 0x00000000 Type R/W RO R/W Description Load Current value Control See page 173 174 175
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171
Watchdog Timer
Table 10-1. WDT Register Map (Continued)
Offset 0x00C 0x010 0x014 0x418 0xC00 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name WDTICR WDTRIS WDTMIS WDTTEST WDTLOCK WDTPeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7 WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID3 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000005 0x00000018 0x00000018 0x00000001 0x0000000D 0x000000F0 0x00000005 0x000000B1 Type WO RO RO R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO Description Interrupt clear Raw interrupt status Masked interrupt status Watchdog stall enable Lock Peripheral identification 4 Peripheral identification 5 Peripheral identification 6 Peripheral identification 7 Peripheral identification 0 Peripheral identification 1 Peripheral identification 2 Peripheral identification 3 PrimeCell identification 0 PrimeCell identification 1 PrimeCell identification 2 PrimeCell identification 3 See page 176 177 178 180 179 181 182 183 184 185 186 187 188 189 190 191 192
10.5
Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address offset.
172 Preliminary
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LM3S102 Data Sheet
Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x00000000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLoad
Type Reset
R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0
WDTLoad
Type Reset
R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1
Bit/Field 31:0
Name WDTLoad
Type R/W
Reset 0xFFFFFFFF
Description Watchdog Load Value
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173
Watchdog Timer
Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTValue
Type Reset
RO 1 15 RO 1 14 RO 1 13 RO 1 12 RO 1 11 RO 1 10 RO 1 9 RO 1 8 RO 1 7 RO 1 6 RO 1 5 RO 1 4 RO 1 3 RO 1 2 RO 1 1 RO 1 0
WDTValue
Type Reset
RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1
Bit/Field 31:0
Name WDTValue
Type RO
Reset 0xFFFFFFFF
Description Watchdog Value Current value of the 32-bit down counter.
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LM3S102 Data Sheet
Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (upon second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
RESEN
R/W 0
INTEN
R/W 0
Bit/Field 31:2
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Reset Enable 0: Disabled. 1: Enable the Watchdog module reset output.
1
RESEN
R/W
0
0
INTEN
R/W
0
Watchdog Interrupt Enable 0: Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset) 1: Interrupt event enabled. Once enabled, all writes are ignored.
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Watchdog Timer
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate.
Watchdog Interrupt Clear (WDTICR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTIntClr
Type Reset
WO 15 WO 14 WO 13 WO 12 WO 11 WO 10 WO 9 WO 8 WO 7 WO 6 WO 5 WO 4 WO 3 WO 2 WO 1 WO 0
WDTIntClr
Type Reset
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO -
Bit/Field 31:0
Name WDTIntClr
Type WO
Reset -
Description Watchdog Interrupt Clear
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October 6, 2006
LM3S102 Data Sheet
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
WDTRIS
RO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR.
0
WDTRIS
RO
0
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177
Watchdog Timer
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
WDTMIS
RO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt.
0
WDTMIS
RO
0
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LM3S102 Data Sheet
Register 7: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACCE551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x00000001 (when locked; otherwise, the returned value is 0x00000000 (unlocked)).
Watchdog Lock (WDTLOCK)
Offset 0xC00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDTLock
Type Reset
R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0
WDTLock
Type Reset
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:0
Name WDTLock
Type R/W
Reset 0x0000
Description Watchdog Lock A write of the value 0x1ACCE551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Locked: 0x00000001 Unlocked: 0x00000000
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Watchdog Timer
Register 8: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug.
Watchdog Test (WDTTEST)
Offset 0x418
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
STALL
R/W 0 RO 0 RO 0 RO 0
reserved
RO 0 RO 0 RO 0 RO 0 RO 0
Bit/Field 31:9
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Stall Enable When set to 1, if the Stellaris microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting.
8
STALL
R/W
0
7:0
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed.
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October 6, 2006
LM3S102 Data Sheet
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Offset 0xFD0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID4
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. WDT Peripheral ID Register[7:0]
7:0
PID4
RO
0x00
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181
Watchdog Timer
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Offset 0xFD4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID5
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. WDT Peripheral ID Register[15:8]
7:0
PID5
RO
0x00
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October 6, 2006
LM3S102 Data Sheet
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Offset 0xFD8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID6
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. WDT Peripheral ID Register[23:16]
7:0
PID6
RO
0x00
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183
Watchdog Timer
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Offset 0xFDC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID7
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. WDT Peripheral ID Register[31:24]
7:0
PID7
RO
0x00
184 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Offset 0xFE0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID0
RO 0 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Peripheral ID Register[7:0]
7:0
PID0
RO
0x05
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185
Watchdog Timer
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Offset 0xFE4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1
PID1
RO 1 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Peripheral ID Register[15:8]
7:0
PID1
RO
0x18
186 Preliminary
October 6, 2006
LM3S102 Data Sheet
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Offset 0xFE8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1
PID2
RO 1 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Peripheral ID Register[23:16]
7:0
PID2
RO
0x18
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187
Watchdog Timer
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Offset 0xFEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID3
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog Peripheral ID Register[31:24]
7:0
PID3
RO
0x01
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LM3S102 Data Sheet
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Primecell Identification 0 (WDTPCellID0)
Offset 0xFF0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
CID0
RO 1 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog PrimeCell ID Register[7:0]
7:0
CID0
RO
0x0D
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Watchdog Timer
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Primecell Identification 1 (WDTPCellID1)
Offset 0xFF4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1
CID1
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog PrimeCell ID Register[15:8]
7:0
CID1
RO
0xF0
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LM3S102 Data Sheet
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Primecell Identification 2 (WDTPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
CID2
RO 0 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog PrimeCell ID Register[23:16]
7:0
CID2
RO
0x05
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Watchdog Timer
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value.
Watchdog Primecell Identification 3 (WDTPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1
CID3
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Watchdog PrimeCell ID Register[31:24]
7:0
CID3
RO
0xB1
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LM3S102 Data Sheet
11
Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550-type serial interface characteristics. The LM3S102 controller is equipped with one UART module. The UART has the following features: Separate transmit and receive FIFOs Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 Programmable baud-rate generator allowing rates up to 460.8 Kbps Standard asynchronous communication bits for start, stop and parity False start bit detection Line-break generation and detection Fully programmable serial interface characteristics: - 5, 6, 7, or 8 data bits - Even, odd, stick, or no-parity bit generation/detection - 1 or 2 stop bit generation
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Universal Asynchronous Receiver/Transmitter (UART)
11.1
Block Diagram
Figure 11-1. UART Module Block Diagram
System Clock
Interrupt
Interrupt Control UARTIFLS UARTIM UARTMIS
TXFIFO 16x8
. . .
Transmitter Baud Rate Generator UARTIBRD UARTFBRD Receiver UnRx UnTx
Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UART PeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7
UARTRIS UARTICR
UARTDR
Control / Status UARTRSR/ECR UARTFR UARTLCRH UARTCTL
RXFIFO 16x8
. . .
11.2
Functional Description
The Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 210). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping.
11.2.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
194 Preliminary
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LM3S102 Data Sheet
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 11-2 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 11-2. UART Character Frame
UnTX 1 0 n Start LSB 5-8 data bits Parity bit if enabled MSB
1-2 stop bits
11.2.2
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 206) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 207). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.):
BRD = BRDI + BRDF = SysClk / (16 * Baud Rate)
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 208), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: UARTIBRD write, UARTFBRD write, and UARTLCRH write UARTFBRD write, UARTIBRD write, and UARTLCRH write UARTIBRD write and UARTLCRH write UARTFBRD write and UARTLCRH write
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11.2.3
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 204) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the U0Rx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in "Transmit/Receive Logic" on page 194). The start bit is valid if U0Rx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 202). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if U0Rx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word.
11.2.4
FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 200). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 208). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 204) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 211). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, 1/4, 1/2, 3/4 and 7/8. For example, if the 1/4 option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the 1/2 mark.
11.2.5
Interrupts
The UART can generate interrupts when the following conditions are observed: Overrun Error Break Error Parity Error Framing Error
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Receive Timeout Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 215). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM) register (see page 212) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 214). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 216).
11.2.6
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 210). In loopback mode, data transmitted on U0Tx is received on the U0Rx input.
11.3
Initialization and Configuration
To use the UART, the peripheral clock must be enabled by setting the UART0 bit in the RCGC1 register. This section discusses the steps that are required for using a UART module. For this example, the system clock is assumed to be 20 MHz and the desired UART configuration is: 115200 baud rate Data length of 8 bits One stop bit No parity FIFOs disabled No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in "Baud-Rate Generation" on page 195, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 206) should be set to 10. The value to be loaded into the UARTFBRD register (see page 207) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register.
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3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x00000060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
11.4
Register Map
Table 11-1 lists the UART registers. The offset listed is a hexadecimal increment to the register's address, relative to that UART's base address: UART0: 0x4000C000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 210) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 11-1. UART Register Map
Offset 0x000 0x004 Name UARTDR UARTRSR UARTECR 0x018 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC UARTFR UARTIBRD UARTFBRD UARTLCRH UARTCTL UARTIFLS UARTIM UARTRIS UARTMIS UARTICR UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 0x00000090 0x00000000 0x00000000 0x00000000 0x00000300 0x00000012 0x00000000 0x0000000F 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000011 0x00000000 0x00000018 0x00000001 RO R/W R/W R/W R/W R/W R/W RO RO W1C RO RO RO RO RO RO RO RO Reset 0x00000000 0x00000000 Type R/W R/W Description Data Receive Status (read) Error Clear (write) Flag Register (read only) Integer Baud-Rate Divisor Fractional Baud-Rate Divisor Line Control Register, High byte Control Register Interrupt FIFO Level Select Interrupt Mask Raw Interrupt Status Masked Interrupt Status Interrupt Clear Peripheral identification 4 Peripheral identification 5 Peripheral identification 6 Peripheral identification 7 Peripheral identification 0 Peripheral identification 1 Peripheral identification 2 Peripheral identification 3 204 206 207 208 210 211 212 214 215 216 217 218 219 220 221 222 223 224 See page 200 202
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Table 11-1. UART Register Map (Continued)
Offset 0xFF0 0xFF4 0xFF8 0xFFC Name UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 Reset 0x0000000D 0x000000F0 0x00000005 0x000000B1 Type RO RO RO RO Description PrimeCell identification 0 PrimeCell identification 1 PrimeCell identification 2 PrimeCell identification 3 See page 225 226 227 228
11.5
Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address offset.
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Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.
UART Data (UARTDR)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0
OE
RO 0
BE
RO 0
PE
RO 0
FE
RO 0 R/W 0 R/W 0 R/W 0
DATA
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:12
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Overrun Error 1=New data was received when the FIFO was full, resulting in data loss. 0=There has been no data loss due to a FIFO overrun.
11
OE
RO
0
10
BE
RO
0
UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a fullword transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received.
9
PE
RO
0
UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO.
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Bit/Field 8
Name FE
Type RO
Reset 0
Description UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1).
7:0
DATA
R/W
0
When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART.
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset.
UART Receive Status (UARTRSR): Read
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
OE
RO 0
BE
RO 0
PE
RO 0
FE
RO 0
UART Error Clear (UARTECR): Write
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 WO 0 2 WO 0 1 WO 0 0
reserved
Type Reset
WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0
DATA
WO 0 WO 0 WO 0 WO 0
Bit/Field
Name
Type
Reset
Description
Read-Only Receive Status (UARTRSR) Register 31:4 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. The UARTRSR register cannot be written. UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO.
3
OE
RO
0
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Bit/Field 2
Name BE
Type RO
Reset 0
Description UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a fullword transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
1
PE
RO
0
UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR.
0
FE
RO
0
UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
Write-Only Error Clear (UARTECR) Register 31:8 reserved WO 0 Reserved bits return an indeterminate value, and should never be changed. A write to this register of any data clears the framing, parity, break and overrun flags.
7:0
DATA
WO
0
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Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1.
UART Flag (UARTFR)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
TXFE
RO 1
RXFF
RO 0
TXFF
RO 0
RXFE
RO 1
BUSY
RO 0 RO 0
reserved
RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty.
7
TXFE
RO
1
6
RXFF
RO
0
UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full.
5
TXFF
RO
0
UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full.
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Bit/Field 4
Name RXFE
Type RO
Reset 1
Description UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty.
3
BUSY
RO
0
UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled).
2:0
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed.
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Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See "Baud-Rate Generation" on page 195 for configuration details.
UART Integer Baud-Rate Divisor
Offset 0x024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
DIVINT
Type Reset
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Integer Baud-Rate Divisor
15:0
DIVINT
R/W
0x0000
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LM3S102 Data Sheet
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See "Baud-Rate Generation" on page 195 for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
Offset 0x028
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0
DIVFRAC
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:6
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Fractional Baud-Rate Divisor
5:0
DIVFRAC
R/W
0x00
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Register 6: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register.
UART Line Control (UARTLCRH)
Offset 0x02C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
SPS
R/W 0
WLEN
R/W 0 R/W 0
FEN
R/W 0
STP2
R/W 0
EPS
R/W 0
PEN
R/W 0
BRK
R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Stick Parity Select When bits 1, 2 and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled.
7
SPS
R/W
0
6:5
WLEN
R/W
0
UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: 0x3: 8 bits 0x2: 7 bits 0x1: 6 bits 0x0: 5 bits (default)
4
FEN
R/W
0
UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.
3
STP2
R/W
0
UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received.
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Bit/Field 2
Name EPS
Type R/W
Reset 0
Description UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit.
1
PEN
R/W
0
UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame.
0
BRK
R/W
0
UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0.
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Register 7: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping.
UART Control (UARTCR)
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
RXE
R/W 1
TXE
R/W 1
LBE
R/W 0 RO 0 RO 0 RO 0
reserved
RO 0 RO 0 RO 0
UARTEN
R/W 0
Bit/Field 31:10
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping.
9
RXE
R/W
1
8
TXE
R/W
1
UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping.
7
LBE
R/W
0
UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path.
6:1
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.
0
UARTEN
R/W
0
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Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
Offset 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0
RXIFLSEL
R/W 1 R/W 0 R/W 0
TXIFLSEL
R/W 1 R/W 0
Bit/Field 31:6
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: 000: RX FIFO 1/8 full 001: RX FIFO 1/4 full 010: RX FIFO 1/2 full (default) 011: RX FIFO 3/4 full 100: RX FIFO 7/8 full 101-111: Reserved
5:3
RXIFLSEL
R/W
0X2
2:0
TXIFLSEL
R/W
0X2
UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: 000: TX FIFO 1/8 full 001: TX FIFO 1/4 full 010: TX FIFO 1/2 full (default) 011: TX FIFO 3/4 full 100: TX FIFO 7/8 full 101-111: Reserved
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Register 9: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
Offset 0x038
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0
OEIM
R/W 0
BEIM
R/W 0
PEIM
R/W 0
FEIM
R/W 0
RTIM
R/W 0
TXIM
R/W 0
RXIM
R/W 0 RO 0
reserved
RO 0 RO 0 RO 0
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
10
OEIM
R/W
0
9
BEIM
R/W
0
UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
8
PEIM
R/W
0
UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
7
FEIM
R/W
0
UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
6
RTIM
R/W
0
UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
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LM3S102 Data Sheet
Bit/Field 5
Name TXIM
Type R/W
Reset 0
Description UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
4
RXIM
R/W
0
UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
3:0
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed.
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Universal Asynchronous Receiver/Transmitter (UART)
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
Offset 0x03C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0
OERIS
RO 0
BERIS
RO 0
PERIS
RO 0
FERIS
RO 0
RTRIS
RO 0
TXRIS
RO 0
RXRIS
RO 0 RO 1 RO 1
reserved
RO 1 RO 1
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt.
10
OERIS
RO
0
9
BERIS
RO
0
UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt.
8
PERIS
RO
0
UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt.
7
FERIS
RO
0
UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt.
6
RTRIS
RO
0
UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt.
5
TXRIS
RO
0
UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt.
4
RXRIS
RO
0
UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt.
3:0
reserved
RO
0xF
This reserved bit is read-only and has a reset value of 0xF.
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LM3S102 Data Sheet
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
Offset 0x040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0
OEMIS
RO 0
BEMIS
RO 0
PEMIS
RO 0
FEMIS
RO 0
RTMIS
RO 0
TXMIS RXMIS
RO 0 RO 0 RO 0 RO 0
reserved
RO 0 RO 0
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt.
10
OEMIS
RO
0
9
BEMIS
RO
0
UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt.
8
PEMIS
RO
0
UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt.
7
FEMIS
RO
0
UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt.
6
RTMIS
RO
0
UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt.
5
TXMIS
RO
0
UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt.
4
RXMIS
RO
0
UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt.
3:0
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed.
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Universal Asynchronous Receiver/Transmitter (UART)
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
Offset 0x044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0
OEIC
W1C 0
BEIC
W1C 0
PEIC
W1C 0
FEIC
W1C 0
RTIC
W1C 0
TXIC
W1C 0
RXIC
W1C 0 RO 0 RO 0
reserved
RO 0 RO 0
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Overrun Error Interrupt Clear 0: No effect on the interrupt. 1: Clears interrupt.
10
OEIC
W1C
0
9
BEIC
W1C
0
Break Error Interrupt Clear 0: No effect on the interrupt. 1: Clears interrupt.
8
PEIC
W1C
0
Parity Error Interrupt Clear 0: No effect on the interrupt. 1: Clears interrupt.
7
FEIC
W1C
0
Framing Error Interrupt Clear 0: No effect on the interrupt. 1: Clears interrupt.
6
RTIC
W1C
0
Receive Time-Out Interrupt Clear 0: No effect on the interrupt. 1: Clears interrupt.
5
TXIC
W1C
0
Transmit Interrupt Clear 0: No effect on the interrupt. 1: Clears interrupt.
4
RXIC
W1C
0
Receive Interrupt Clear 0: No effect on the interrupt. 1: Clears interrupt.
3:0
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed.
216 Preliminary
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LM3S102 Data Sheet
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
Offset 0xFD0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID4
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[7:0]
7:0
PID4
RO
0x00
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217
Universal Asynchronous Receiver/Transmitter (UART)
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
Offset 0xFD4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID5
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[15:8]
7:0
PID5
RO
0x00
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LM3S102 Data Sheet
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
Offset 0xFD8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID6
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[23:16]
7:0
PID6
RO
0x00
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Universal Asynchronous Receiver/Transmitter (UART)
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
Offset 0xFDC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID7
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[31:24]
7:0
PID7
RO
0x00
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LM3S102 Data Sheet
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
Offset 0xFE0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1
PID0
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral.
7:0
PID0
RO
0x11
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221
Universal Asynchronous Receiver/Transmitter (UART)
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
Offset 0xFE4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID1
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral.
7:0
PID1
RO
0x00
222 Preliminary
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LM3S102 Data Sheet
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
Offset 0xFE8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1
PID2
RO 1 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral.
7:0
PID2
RO
0x18
October 6, 2006 Preliminary
223
Universal Asynchronous Receiver/Transmitter (UART)
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
Offset 0xFEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID3
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral.
7:0
PID3
RO
0x01
224 Preliminary
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LM3S102 Data Sheet
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Primecell Identification 0 (UARTPCellID0)
Offset 0xFF0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
CID0
RO 1 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system.
7:0
CID0
RO
0x0D
October 6, 2006 Preliminary
225
Universal Asynchronous Receiver/Transmitter (UART)
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Primecell Identification 1 (UARTPCellID1)
Offset 0xFF4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1
CID1
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system.
7:0
CID1
RO
0xF0
226 Preliminary
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LM3S102 Data Sheet
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Primecell Identification 2 (UARTPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
CID2
RO 0 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system.
7:0
CID2
RO
0x05
October 6, 2006 Preliminary
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Universal Asynchronous Receiver/Transmitter (UART)
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values.
UART Primecell Identification 3 (UARTPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1
CID3
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system.
7:0
CID3
RO
0xB1
228 Preliminary
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LM3S102 Data Sheet
12
Synchronous Serial Interface (SSI)
The Stellaris Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris SSI has the following features: Master or slave operation Programmable clock bit rate and prescale Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces Programmable data frame size from 4 to 16 bits Internal loopback test mode for diagnostic/debug testing
12.1
Block Diagram
SSI Module Block Diagram
Interrupt Interrupt Control SSIIM SSIMIS Control / Status SSICR0 SSICR1 SSISR SSIDR RxFIFO 8 x 16 System Clock Clock Prescaler Identification Registers SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 SSIPeriphID 0 SSIPeriphID 1 SSIPeriphID 2 SSIPeriphID 3 SSIPeriphID 4 SSIPeriphID 5 SSIPeriphID 6 SSIPeriphID 7 SSICPSR Transmit / Receive Logic SSIRIS SSIICR TxFIFO 8 x 16
Figure 12-1.
. . .
SSITx SSIRx SSIClk SSIFss
. . .
October 6, 2006 Preliminary
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Synchronous Serial Interface (SSI)
12.2
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes.
12.2.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 1.5 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the 20-MHz input clock. The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 247). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 241). The frequency of the output clock SSIClk is defined by:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note that although the SSIClk transmit clock can theoretically be 10 MHz, the module may not be able to operate at that speed. For transmit operations, the system clock must be at least two times faster than the SSIClk. For receive operations, the system clock must be at least 12 times faster than the SSIClk. See "Electrical Characteristics" on page 316 to view SSI timing parameters.
12.2.2
12.2.2.1
FIFO Operation
Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 245), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
12.2.2.2
Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively.
12.2.3
Interrupts
The SSI can generate interrupts when the following conditions are observed: Transmit FIFO service Receive FIFO service Receive FIFO time-out Receive FIFO overrun
230 Preliminary
October 6, 2006
LM3S102 Data Sheet
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 248). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 249 and page 250, respectively).
12.2.4
Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: Texas Instruments synchronous serial Freescale SPI MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits.
12.2.4.1
Texas Instruments Synchronous Serial Frame Format Figure 12-2 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk SSIFss SSITx/SSIRx MSB 4 to 16 bits LSB
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Synchronous Serial Interface (SSI)
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 12-3 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSIClk SSIFss SSITx/SSIRx
MSB 4 to 16 bits LSB
12.2.4.2
Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
12.2.4.3
Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 12-4 and Figure 12-5.
232 Preliminary
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LM3S102 Data Sheet
Figure 12-4.
SSIClk SSIFss SSIRx
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
MSB 4 to 16 bits
LSB
Q
SSITx
MSB
LSB
Figure 12-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk SSIFss SSIRx LSB MSB 4 to 16 bits SSITx LSB MSB LSB MSB LSB MSB
In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 12.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 12-6, which covers both single and continuous transfers.
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Figure 12-6.
SSIClk SSIFss SSIRx Q
Freescale SPI Frame Format with SPO=0 and SPH=1
MSB 4 to 16 bits MSB
LSB LSB
Q
SSITx
In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 12-7 and Figure 12-8. Figure 12-7.
SSIClk SSIFss SSIRx MSB 4 to 16 bits SSITx MSB LSB LSB Q
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
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Figure 12-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk SSIFss SSITx/SSIRx LSB MSB 4 to 16 bits LSB MSB
In this configuration, during idle periods: SSIClk is forced High SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 12.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 12-9, which covers both single and continuous transfers. Figure 12-9.
SSIClk SSIFss SSIRx Q MSB 4 to 16 bits SSITx MSB LSB LSB Q
Freescale SPI Frame Format with SPO=1 and SPH=1
Note:
Q is undefined in Figure 12-9.
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In this configuration, during idle periods: SSIClk is forced High SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low When the SSI is configured as a master, it enables the SSIClk pad When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 12.2.4.7 MICROWIRE Frame Format Figure 12-10 shows the MICROWIRE frame format, again for a single frame. Figure 12-11 shows the same format when back-to-back frames are transmitted. Figure 12-10.
SSIClk SSIFss SSITx SSIRx
MSB LSB
MICROWIRE Frame Format (Single Frame)
8-bit control 0
MSB LSB
4 to 16 bits output data
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: SSIClk is forced Low SSIFss is forced High The transmit data line SSITx is arbitrarily forced Low
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A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. Figure 12-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk SSIFss SSITx
LSB MSB LSB
8-bit control SSIRx 0
MSB LSB MSB
4 to 16 bits output data
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 12-12 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period.
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Figure 12-12.
MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
tSetup =(2*tSSIClk ) tHold=tSSIClk SSIClk SSIFss SSIRx
First RX data to be sampled by SSI slave
12.3
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x00000000. b. For slave mode (output enabled), set the SSICR1 register to 0x00000004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 4. Write the SSICR0 register with the following configuration: - Serial clock rate (SCR) - Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) - The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) - The data size (DSS) 5. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: Master operation Freescale SPI mode (SPO=1, SPH=1) 1 Mbps bit rate 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) ' 1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x00000000.
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3. Write the SSICPSR register with a value of 0x00000002. 4. Write the SSICR0 register with a value of 0x000009C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
12.4
Register Map
Table 12-1 lists the SSI registers. The offset listed is a hexadecimal increment to the register's address, relative to the SSI base address of 0x40008000. Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed.
Table 12-1. SSI Register Map
Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name SSICR0 SSICR1 SSIDR SSISR SSICPSR SSIIM SSIRIS SSIMIS SSIICR SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 Reset 0x00000000 0x00000000 0x00000000 0x00000003 0x00000000 0x00000000 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000022 0x00000000 0x00000018 0x00000001 0x0000000D 0x000000F0 0x00000005 0x000000B1 Type RW RW RW RO RW RW RO RO W1C RO RO RO RO RO RO RO RO RO RO RO RO Description Control 0 Control 1 Data Status Clock prescale Interrupt mask Raw interrupt status Masked interrupt status Interrupt clear Peripheral identification 4 Peripheral identification 5 Peripheral identification 6 Peripheral identification 7 Peripheral identification 0 Peripheral identification 1 Peripheral identification 2 Peripheral identification 3 PrimeCell identification 0 PrimeCell identification 1 PrimeCell identification 2 PrimeCell identification 3 See page 241 243 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263
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12.5
Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate and data size are configured in this register.
SSI Control 0 (SSICR0)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
SCR
Type Reset
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
SPH
R/W 0
SPO
R/W 0 R/W 0
FRF
R/W 0 R/W 0 R/W 0
DSS
R/W 0 R/W 0
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR= FSSICLK/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255.
15:8
SCR
R/W
0
7
SPH
R/W
0
SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition.
6
SPO
R/W
0
SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on the SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred.
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Bit/Field 5:4
Name FRF
Type R/W
Reset 0
Description SSI Frame Format Select. The FRF values are defined as follows: FRF Value 00 01 10 11 Frame Format Freescale SPI Frame Format Texas Instruments Synchronous Serial Frame Format MICROWIRE Frame Format Reserved
3:0
DSS
R/W
0
SSI Data Size Select The DSS values are defined as follows: DSS Value 0000-0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Data Size Reserved 4-bit data 5-bit data 6-bit data 7-bit data 8-bit data 9-bit data 10-bit data 11-bit data 12-bit data 13-bit data 14-bit data 15-bit data 16-bit data
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Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSCR1)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
SOD
R/W 0
MS
R/W 0
SSE
R/W 0
LBM
R/W 0
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. 0: SSI can drive SSITx output in Slave Output mode. 1: SSI must not drive the SSITx output in Slave mode.
3
SOD
R/W
0
2
MS
R/W
0
SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). 0: Device configured as a master. 1: Device configured as a slave.
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Bit/Field 1
Name SSE
Type R/W
Reset 0
Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. 0: SSI operation disabled. 1: SSI operation enabled. Note: This bit must be set to 0 before any control registers are reprogrammed.
0
LBM
R/W
0
SSI Loopback Mode Setting this bit enables Loopback Test mode. 0: Normal serial port operation enabled. 1: Output of the transmit serial shift register is connected internally to the input of the receive serial shift register.
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LM3S102 Data Sheet
Register 3: SSI Data (SSIDR), offset 0x008 SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
DATA
Type Reset
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:16
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data.
15:0
DATA
R/W
0
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Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
BSY
RO 0
RFF
RO 0
RNE
RO 0
TNF
RO 1
TFE
RO 1
Bit/Field 31:5
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Busy Bit 0: SSI is idle. 1: SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty.
4
BSY
RO
0
3
RFF
RO
0
SSI Receive FIFO Full 0: Receive FIFO is not full. 1: Receive FIFO is full.
2
RNE
RO
0
SSI Receive FIFO Not Empty 0: Receive FIFO is empty. 1: Receive FIFO is not empty.
1
TNF
RO
1
SSI Transmit FIFO Not Full 0: Transmit FIFO is full. 1: Transmit FIFO is not full.
0
TFE
R0
1
SSI Transmit FIFO Empty 0: Transmit FIFO is not empty. 1: Transmit FIFO is empty.
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LM3S102 Data Sheet
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
CPSDVSR
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads.
7:0
CPSDVSR
R/W
0
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask.
SSI Interrupt Mask (SSIIM)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
TXIM
R/W 0
RXIM
R/W 0
RTIM
R/W 0
RORIM
R/W 0
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Transmit FIFO Interrupt Mask 0: TX FIFO half-full or less condition interrupt is masked. 1: TX FIFO half-full or less condition interrupt is not masked.
3
TXIM
R/W
0
2
RXIM
R/W
0
SSI Receive FIFO Interrupt Mask 0: RX FIFO half-full or more condition interrupt is masked. 1: RX FIFO half-full or more condition interrupt is not masked.
1
RTIM
R/W
0
SSI Receive Time-Out Interrupt Mask 0: RX FIFO time-out interrupt is masked. 1: RX FIFO time-out interrupt is not masked.
0
RORIM
R/W
0
SSI Receive Overrun Interrupt Mask 0: RX FIFO overrun interrupt is masked. 1: RX FIFO overrun interrupt is not masked.
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LM3S102 Data Sheet
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
TXRIS
RO 1
RXRIS
RO 0
RTRIS RORRIS
RO 0 RO 0
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half full or less, when set.
3
TXRIS
RO
1
2
RXRIS
RO
0
SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half full or more, when set.
1
RTRIS
RO
0
SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set.
0
RORRIS
RO
0
SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set.
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Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
Offset 0x01C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
TXMIS RXMIS
RO 0 RO 0
RTMIS RORMIS
RO 0 RO 0
Bit/Field 31:4
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half full or less, when set.
3
TXMIS
RO
0
2
RXMIS
RO
0
SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half full or more, when set.
1
RTMIS
RO
0
SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set.
0
RORMIS
RO
0
SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set.
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LM3S102 Data Sheet
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
RTIC
W1C 0
RORIC
W1C 0
Bit/Field 31:2
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Receive Time-Out Interrupt Clear 0: No effect on interrupt. 1: Clears interrupt.
1
RTIC
W1C
0
0
RORIC
W1C
0
SSI Receive Overrun Interrupt Clear 0: No effect on interrupt. 1: Clears interrupt.
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Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Peripheral Identification 4 (SSIPeriphID4)
Offset 0xFD0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID4
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[7:0]
7:0
PID4
RO
0x00
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LM3S102 Data Sheet
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Peripheral Identification 5 (SSIPeriphID5)
Offset 0xFD4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID5
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[15:8]
7:0
PID5
RO
0x00
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Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Peripheral Identification 6 (SSIPeriphID6)
Offset 0xFD8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID6
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[23:16]
7:0
PID6
RO
0x00
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Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Peripheral Identification 7 (SSIPeriphID7)
Offset 0xFDC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID7
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[31:24]
7:0
PID7
RO
0x00
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Synchronous Serial Interface (SSI)
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Peripheral Identification 0 (SSIPeriphID0)
Offset 0xFEO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0
PID0
RO 0 RO 0 RO 1 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral.
7:0
PID0
RO
0x22
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LM3S102 Data Sheet
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Peripheral Identification 1 (SSIPeriphID1)
Offset 0xFE4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID1
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral.
7:0
PID1
RO
0x00
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Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Peripheral Identification 2 (SSIPeriphID2)
Offset 0xFE8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1
PID2
RO 1 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral.
7:0
PID2
RO
0x18
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LM3S102 Data Sheet
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Peripheral Identification 3 (SSIPeriphID3)
Offset 0xFEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
PID3
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral.
7:0
PID3
RO
0x01
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Synchronous Serial Interface (SSI)
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Primecell Identification 0 (SSIPCellID0)
Offset 0xFF0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
CID0
RO 1 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system.
7:0
CID0
RO
0x0D
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LM3S102 Data Sheet
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Primecell Identification 1 (SSIPCellID1)
Offset 0xFF4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1
CID1
RO 0 RO 0 RO 0 RO 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system.
7:0
CID1
RO
0xF0
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Synchronous Serial Interface (SSI)
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Primecell Identification 2 (SSIPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
CID2
RO 0 RO 1 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system.
7:0
CID2
RO
0x05
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LM3S102 Data Sheet
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value.
SSI Primecell Identification 3 (SSIPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1
CID3
RO 0 RO 0 RO 0 RO 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system.
7:0
CID3
RO
0xB1
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Inter-Integrated Circuit (I2C) Interface
13
Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDL and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The Stellaris I2C module provides the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master.
13.1
Block Diagram
Figure 13-1. I2C Block Diagram
I2C Control I2CMSA I2CMCS I2CMDR Interrupt I2CMTPR I2CMIMR I2CMRIS I2CMMIS I2CMICR I2CMCR I2CSOAR I2CSCSR I2CSDR I2CSIM I2CSRIS I2CSMIS I2CSICR I2C Slave Core I2C Master Core
I2CSCL
I2CSDA I2CSCL I2C I/O Select I2CSDA I2CSCL
I2CSDA
13.2
Functional Description
The I2C module is comprised of both a master and slave function. The master and slave functions are implemented as separate peripherals. The I2C module must be connected to bi-directional Open-Drain pads. A typical I2C bus configuration is shown in Figure 13-2. See "I2C Timing" on page 321 for I2C timing diagrams.
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LM3S102 Data Sheet
Figure 13-2.
I2C Bus Configuration
RPUP RPUP
SCL SDA
I2CSCL I2CSDA
I2C Bus
SCL SDA SCL SDA
StellarisTM
3rd Party Device with I2C Interface
3rd Party Device with I2C Interface
13.2.1
I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line.
13.2.1.1
Data Transfers Both the SDA and SCL lines are bi-directional, connected to the positive supply via pull-up resistors. The bus is idle or free, when both lines are High. The output devices (pad drivers) must have an open-drain configuration. Data on the I2C bus can be transferred at rates up to 100 Kbps in Standard mode and up to 400 Kbps in Fast mode.
13.2.1.2
Data Validity The data on the SDA line must be stable during the High period of the clock. The data line can only change when the clock SCL is in its Low state (see Figure 13-3). Figure 13-3. Data Validity During Bit Transfer on the I2C Bus
SDA
SCL
ge Data line Chan stable of data allowed
13.2.1.3
START and STOP Conditions The protocol of the I2C bus defines two states: START and STOP. A High-to-Low transition on the SDA line while the SCL is High is a START condition. A Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition. The bus is considered busy after a START condition. The bus is considered free after a STOP condition. See Figure 13-4. Figure 13-4.
SDA SCL
START condition STOP condition
START and STOP Conditions
SDA SCL
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Inter-Integrated Circuit (I2C) Interface
13.2.1.4
Byte Format Every byte put out on the SDA line must be 8-bits long. The number of bytes per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
13.2.1.5
Acknowledge Data transfer with an acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse. The receiver must pull down SDA during the acknowledge clock pulse such that it remains stable (Low) during the High period of the acknowledge clock pulse. When a slave receiver does not acknowledge the slave address, the data line must be left in a High state by the slave. The master can then generate a STOP condition to abort the current transfer. If the master receiver is involved in the transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the SDA line to allow the master to generate the STOP or a repeated START condition.
13.2.1.6
Arbitration A master may start a transfer only if the bus is idle. Two or more masters may generate a START condition within minimum hold time of the START condition. Arbitration takes place on the SDA line, while SCL is in the High state, in such a manner that the master transmitting a High level (while another master is transmitting a Low level) will switch off its data output stage. Arbitration can be over several bits. Its first stage is a comparison of address bits. If both masters are trying to address the same device, arbitration continues with comparison of data bits.
13.2.1.7
Data Format with 7-Bit Address Data transfers follow the format shown in Figure 13-5. After the START condition, a slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). A zero indicates a transmission (Send); a one indicates a request for data (Receive). A data transfer is always terminated by a STOP condition generated by the master. However, a master can still communicate on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/send formats are then possible within such a transfer.
Figure 13-5.
SDA
Complete Data Transfer with a 7-Bit Address
MSB LSB R/S ACK MSB LSB ACK
SCL
1
2
Slave address
7
8
9
1
2
Data
7
8
9
The first seven bits of the first byte make up the slave address (see Figure 13-6). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master will write (send) information to a selected slave. A one in this position means that the master will receive information from the slave.
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LM3S102 Data Sheet
Figure 13-6.
R/S Bit in First Byte
MSB
LSB R/S Slave address
13.2.1.8
I2C Master Command Sequences Figure 13-7 through Figure 13-12 present the command sequences available for the I2C master.
Figure 13-7.
Master Single SEND
Idle
write Slave Address to I2CMSA
write DATA to to I2CMDR
Sequence may be omitted in a Single Master system
read I2CMCS
N
Bus Busy=0Y
write "---0-111" to I2CMSA
read I2CMCS
N
Bus Busy=0 Y
Error Service
N
Error=0
Y
Idle
Idle
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Inter-Integrated Circuit (I2C) Interface
Figure 13-8.
Master Single RECEIVE
Idle
write Slave Address to I2CMSA
Sequence may be omitted in a Single Master system
read I2CMCS
N
Bus Busy=0Y
write "---0-111" to I2CMSA
read I2CMCS
N
Bus Busy=0Y
Error Service
N
Error=0
Y
read Data from I2CMDR
Idle
Idle
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LM3S102 Data Sheet
Figure 13-9.
Master Burst SEND
Idle
write Slave Address to I2CMSA
write DATA to to I2CMDR
Sequence may be omitted in a Single Master system
read I2CMCS
N
Bus Busy=0 Y
write "---0-011" to I2CMSA
read I2CMCS
N
Bus Busy=0Y
N
Error=0
write "---0-001" to I2CMSA Y
write "---0-100 to I2CMCS
Y N Arb_Lost="1"
write DATA to I2CMDR
Error Service Y Error Service Index=n N
Idle
Idle
write "---0-101" to I2CMSA
read I2CMCS
N
Busy=0
Y
Error Service
N
Error=0
Y
Idle
Idle
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Inter-Integrated Circuit (I2C) Interface
Figure 13-10.
Master Burst RECEIVE
Idle
write Slave Address to I2CMSA
Sequence may be omitted in a Single Master system
read I2CMCS
N
Bus Busy=0 Y
write "---01011" to I2CMSA
read I2CMCS
N
Bus Busy=0 Y
N
Error=0
Y
write "---0-100 to I2CMCS
Y N Arb_Lost="1"
read DATA from I2CMDR
Error Service Y Index=m-1 Error Service N write "---01001" to I2CMSA
Idle
Idle
write "---0-101" to I2CMSA
read I2CMCS
N
Busy=0
Y
Error Service
N
Error=0
Y
read DATA from I2CMDR
Idle
Idle
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LM3S102 Data Sheet
Figure 13-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in master TRANSMIT mode STOP condition is not generated
write Slave Address I2CMSA
write "---01011" to I2CMCS REPEATED START condition is generated with changing Data direction Master operates in master RECEIVE mode
Idle
Figure 13-12.
Master Burst SEND after Burst RECEIVE
Idle
Master operates in master RECEIVE mode STOP condition is not generated
write Slave Address I2CMSA
write "---0-011" to I2CMCS REPEATED START condition is generated with changing Data direction Master operates in master TRANSMIT mode
Idle
13.2.1.9
I2C Slave Command Sequences Figure 13-13 presents the command sequence available for the I2C slave.
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Inter-Integrated Circuit (I2C) Interface
Figure 13-13.
Slave Command Sequence
Idle
write OWN Slave address to I2CSOAR
write "-------1" to I2CSCSR
read I2CSCSR
N RREQ="1" Y
read Data from I2CSDR
N
TREQ="1" Y
write Data to I2CSDR
13.2.2
Available Speed Modes
The SCL clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP. where:
CLK_PRD is the system clock period SCL_LP is the Low phase of the SCL clock (fixed at 6) SCL_HP is the High phase of the SCL clock (fixed at 4) TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 282). The SCL clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns TIMER_PRD = 2 SCL_LP=6 SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
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LM3S102 Data Sheet
Table 13-1 gives examples of Timer period, system clock, and speed mode (Standard or Fast). Table 13-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock 4 Mhz 6 Mhz 12.5 Mhz 16.7 Mhz 20 Mhz Timer Period 0x01 0x02 0x06 0x08 0x09 Standard Mode 100 Kbps 100 Kbps 89 Kbps 93 Kbps 100 Kbps Timer Period 0x01 0x02 0x02 Fast Mode 312 Kbps 278 Kbps 333 Kbps
13.3
Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master. This assumes the system clock is 20 MHz. 1. Enable the I2C clock by writing a value of 0x00001000 to the RCGC1 register in the System Control module. 2. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation. 3. Initialize the I2C Master by writing the I2CMCR register with a value of 0x00000020. 4. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation:
TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1; TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1; TPR = 9
Write the I2CMTPR register with the value of 0x00000009. 5. Specify the slave address of the master and that the next operation will be a Send by writing the I2CMSA register with a value of 0x00000076. This sets the slave address to 0x3B. 6. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired data. 7. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with a value of 0x00000007 (STOP, START, RUN). 8. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has been cleared.
13.4
Register Map
Table 13-2 lists the I2C registers. All addresses given are relative to the I2C base addresses for the master and slave: I2C Master: 0x40020000
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Inter-Integrated Circuit (I2C) Interface
I2C Slave: 0x40020800 Table 13-2. I2C Register Map
Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 Name I2CMSA I2CMCS I2CMDR I2CMTPR I2CMIMR I2CMRIS I2CMMIS I2CMICR I2CMCR I2CSOAR I2CSCSR I2CSDR I2CSIMR I2CSRIS I2CSMIS I2CSICR Reset 0x00000000 0x00000000 0x00000000 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Type R/W R/W R/W R/W R/W RO RO WO R/W R/W RO R/W R/W RO RO WO Description Master slave address Master control/status Master data Master timer period Master interrupt mask Master raw interrupt status Master masked interrupt status Master interrupt clear Master configuration Slave address Slave control/status Slave data Slave interrupt mask Slave raw interrupt status Slave masked interrupt status Slave interrupt clear See page 275 276 281 282 283 284 284 285 286 288 289 291 292 293 294 295
13.5
Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. See also "Register Descriptions (I2C Slave)" on page 288.
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LM3S102 Data Sheet
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
SA
R/W 0 R/W 0 R/W 0 R/W 0
R/S
R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. I2C Slave Address This field specifies bits A6 through A0 of the slave address.
7:1
SA
R/W
0
0
R/S
R/W
0
Receive/Send The R/S bit specifies if the next operation is a Receive (High) or Send (Low). 0: Send 1: Receive
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses four control bits when written, and accesses seven status bits when read. The status register consists of seven bits, which when read determine the state of the I2C bus controller. The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes the generation of the START, or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst. To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after each byte. This bit must be reset when the I2C bus controller requires no further data to be sent from the slave transmitter.
I2C Master Status (I2CMCS): Read
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
BUSBSY
RO 0
IDLE
RO 0
ARBLST DATACK ADRACK ERROR
RO 0 RO 0 RO 0 RO 0
BUSY
RO 0
I2C Master Control (I2CMCS): Write
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
ACK
WO 0
STOP
WO 0
START
WO 0
RUN
WO 0
Bit/Field
Name
Type
Reset
Description
Read-Only Status Register 31:7 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. This bit specifies the state of the I2C bus. If set, the bus is busy; otherwise, the bus is idle. The bit changes based on the START and STOP conditions. This bit specifies the I2C controller state. If set, the controller is idle; otherwise the controller is not idle.
6
BUSBSY
R
0
5
IDLE
R
0
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LM3S102 Data Sheet
Bit/Field 4
Name ARBLST
Type R
Reset 0
Description This bit specifies the result of bus arbitration. If set, the controller lost arbitration; otherwise, the controller won arbitration. This bit specifies the result of the last data operation. If set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. This bit specifies the result of the last address operation. If set, the transmitted address was not acknowledged; otherwise, the address was acknowledged. This bit specifies the result of the last bus operation. If set, an error occurred on the last operation; otherwise, no error was detected. The error can be from the slave address not being acknowledged, the transmit data not being acknowledged, or because the controller lost arbitration. This bit specifies the state of the controller. If set, the controller is busy; otherwise, the controller is idle. When the BUSY bit is set, the other status bits are not valid.
3
DATACK
R
0
2
ADRACK
R
0
1
ERROR
R
0
0
BUSY
R
0
Write-Only Control Register 31:7 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. Write reserved. When set, causes received data byte to be acknowledged automatically by the master. See field decoding in Table 13-3 on page 278. When set, causes the generation of the STOP condition. See field decoding in Table 13-3. When set, causes the generation of a START or repeated START condition. See field decoding in Table 13-3. When set, allows the master to send or receive data. See field decoding in Table 13-3.
6-4 3
reserved ACK
W W
0 0
2
STOP
W
0
1
START
W
0
0
RUN
W
0
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Table 13-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
Current State Idle I2CMSA[0] R/S 0 ACK Xa I2CMCS[3:0] Description STOP 0 START 1 RUN 1 START condition followed by SEND (master goes to the Master Transmit state). START condition followed by a SEND and STOP condition (master remains in Idle state). START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive state). START condition followed by RECEIVE and STOP condition (master remains in Idle state). START condition followed by RECEIVE (master goes to the Master Receive state). Illegal. NOP.
0
X
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
All other combinations not listed are non-operations.
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LM3S102 Data Sheet
Table 13-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 2 of 3)
Current State Master Transmit I2CMSA[0] R/S X X X 0 ACK X X X X I2CMCS[3:0] Description STOP 0 1 1 0 START 0 0 0 1 RUN 1 0 1 1 SEND operation (master remains in Master Transmit state). STOP condition (master goes to Idle state). SEND followed by STOP condition (master goes to Idle state). Repeated START condition followed by a SEND (master remains in Master Transmit state). Repeated START condition followed by SEND and STOP condition (master goes to Idle state). Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state). Repeated START condition followed by a SEND and STOP condition (master goes to Idle state). Repeated START condition followed by RECEIVE (master goes to Master Receive state). Illegal. NOP.
0
X
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
All other combinations not listed are non-operations.
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Table 13-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 3 of 3)
Current State Master Receive I2CMSA[0] R/S X X X X X 1 ACK 0 X 0 1 1 0 I2CMCS[3:0] Description STOP 0 1 1 0 1 0 START 0 0 0 0 0 1 RUN 1 0 1 1 1 1 RECEIVE operation with negative ACK (master remains in Master Receive state). STOP condition (master goes to Idle state).b RECEIVE followed by STOP condition (master goes to Idle state). RECEIVE operation (master remains in Master Receive state). Illegal. Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state). Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state). Repeated START condition followed by RECEIVE (master remains in Master Receive state). Repeated START condition followed by SEND (master goes to Master Transmit state). Repeated START condition followed by SEND and STOP condition (master goes to Idle state). NOP.
1
0
1
1
1
1
1
0
1
1
0
X
0
1
1
0
X
1
1
1
All other combinations not listed are non-operations.
a. An X in a table cell indicates that applies to a bit set to 0 or 1. b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave.
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LM3S102 Data Sheet
Register 3: I2C Master Data (I2CMDR), offset 0x008 This register contains the data to be transmitted when in the Master Transmit state, and the data received when in the Master Receive state.
I2C Master Data (I2CMDR)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
DATA
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Data transferred during transaction.
7:0
DATA
R/W
0x00
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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock
I2C Master Timer Period (I2CMTPR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0
TPR
R/W 0 R/W 0 R/W 0 R/W 1
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This field specifies the period of the SCL clock. SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 255). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4).
7:0
TPR
R/W
0x1
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LM3S102 Data Sheet
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
IM
R/W 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked.
0
IM
R/W
0
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Inter-Integrated Circuit (I2C) Interface
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
RIS
RO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit specifies the raw interrupt state (prior to masking) of the I2C master block. If set, an interrupt is pending; otherwise, an interrupt is not pending.
0
RIS
RO
0
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LM3S102 Data Sheet
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
MIS
RO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit specifies the raw interrupt state (after masking) of the I2C master block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared.
0
MIS
RO
0
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Inter-Integrated Circuit (I2C) Interface
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
Offset 0x01C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
IC
WO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Interrupt Clear This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise, a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data.
0
IC
WO
0
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LM3S102 Data Sheet
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
SFE
R/W 0
MFE
R/W 0 RO 0
reserved
RO 0 RO 0
LPBK
R/W 0
Bit/Field 31:6
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. I2C Slave Function Enable This bit specifies whether the interface may operate in Slave mode. If set, Slave mode is enabled; otherwise, Slave mode is disabled.
5
SFE
R/W
0
4
MFE
R/W
0
I2C Master Function Enable This bit specifies whether the interface may operate in Master mode. If set, Master mode is enabled; otherwise, Master mode is disabled and the interface clock is disabled.
3:1
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. I2C Loopback This bit specifies whether the interface is operating normally or in Loopback mode. If set, the device is put in a test mode loopback configuration; otherwise, the device operates normally.
0
LPBK
R/W
0
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Inter-Integrated Circuit (I2C) Interface
13.6
Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. See also "Register Descriptions (I2C Master)" on page 274. Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus.
I2C Slave Own Address Register (I2CSOAR)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
OAR
R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:7
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. I2C Slave Own Address This field specifies bits A6 through A0 of the slave address.
6:0
OAR
R/W
0
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LM3S102 Data Sheet
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 This register accesses one control bit when written, and two status bits when read. The read-only Status register consists of two bits: the RREQ bit and the TREQ bit. The Receive Request (RREQ) bit indicates that the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the I2C Slave Data (I2CSDR) register. The Transmit Request (TREQ) bit indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte into theI2C Slave Data (I2CSDR) register. The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the Stellaris I2C slave operation.
I2C Slave Status Register (I2CSCSR): Read
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
TREQ
RO 0
RREQ
RO 0
I2C Slave Control Register (I2CSCSR): Write
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
DA
WO 0
Bit/Field
Name
Type
Reset
Description
Read-Only Status Register 31:2 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. This bit specifies the state of the I2C slave with regards to outstanding transmit requests. If set, the I2C unit has been addressed as a slave transmitter and uses clock stretching to delay the master until data has been written to the I2CSDR register. Otherwise, there is no outstanding transmit request.
1
TREQ
RO
0
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Inter-Integrated Circuit (I2C) Interface
Bit/Field 0
Name RREQ
Type RO
Reset 0
Description Receive Request This bit specifies the status of the I2C slave with regards to outstanding receive requests. If set, the I2C unit has outstanding receive data from the I2C master and uses clock stretching to delay the master until the data has been read from the I2CSDR register. Otherwise, no receive data is outstanding.
Write-Only Control Register 31:1 reserved RO 0 Reserved bits return an indeterminate value, and should never be changed. Device Active 1=Enables the I2C slave operation. 0=Disables the I2C slave operation.
0
DA
WO
0
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LM3S102 Data Sheet
Register 12: I2C Slave Data (I2CSDR), offset 0x008 This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0
DATA
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Bit/Field 31:8
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This field contains the data for transfer during a slave receive or transmit operation.
7:0
DATA
R/W
0x0
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Inter-Integrated Circuit (I2C) Interface
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
IM
R/W 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked.
0
IM
R/W
0
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LM3S102 Data Sheet
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
RIS
RO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit specifies the raw interrupt state (prior to masking) of the I2C slave block. If set, an interrupt is pending; otherwise, an interrupt is not pending.
0
RIS
RO
0
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Inter-Integrated Circuit (I2C) Interface
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
MIS
RO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit specifies the raw interrupt state (after masking) of the I2C slave block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared.
0
MIS
RO
0
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LM3S102 Data Sheet
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 This register clears the raw interrupt.
I2C Slave Interrupt Clear (I2CSICR)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
IC
WO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data.
0
IC
WO
0
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Analog Comparator
14
Analog Comparator
An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S102 controller provides one analog comparator that can be configured to drive an output or generate an interrupt. A comparator can compare a test voltage against any one of these voltages: An individual external reference voltage A shared single external reference voltage A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts to cause it to start capturing a sample sequence. The interrupt generation logic is separate.
14.1
Block Diagram
Figure 14-1. Analog Comparator Module Block Diagram
C0C0+ -ve input +ve input Comparator 0 output C0o
+ve input (alternate) ACCTL0 ACSTAT0 interrupt reference input interrupt
Voltage Ref internal bus ACREFCTL
14.2
Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module) for the analog input pin be disabled to prevent excessive current draw from the I/O pads. The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT. As shown in Figure 14-2, the input source for VIN- is an external input. In addition to an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
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LM3S102 Data Sheet
Figure 14-2.
Structure of Comparator Unit
-ve input +ve input
0
output CINV IntGen
+ve input (alternate)
1
reference input
2
ACCTL
ACSTAT
A comparator is configured through two status/control registers (ACCTL and ACSTAT). The internal reference is configured through one control register (ACREFCTL). Interrupt status and control is configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the comparators are shown in Table 14-1. Typically, the comparator output is used internally to generate controller interrupts. It may also be used to drive an external pin. Important: Certain register bit values must be set before using the analog comparators. The proper pad configuration for the comparator input and output pins are described in Table 8-1 on page 104. Table 14-1. Comparator 0 Operating Modes
ACCNTL0 ASRCP 00 01 10 11 VINC0C0C0C0VIN+ C0+ C0+ Vref reserved Comparator 0 Output C0o C0o C0o C0o Interrupt yes yes yes yes
14.2.1
Internal Reference Programming
The structure of the internal reference is shown in Figure 14-3. This is controlled by a single configuration register (ACREFCTL). Table 14-2 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally.
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internal bus
297
Analog Comparator
Figure 14-3.
Comparator Internal Reference Structure
AVDD 8R R R *** EN 15 VREF RNG 14 *** Decoder 1 0 internal reference R R 8R
Table 14-2. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register Output Reference Voltage Based on VREF Field Value EN Bit Value EN=0 EN=1 RNG Bit Value RNG=X RNG=0 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the least noisy ground reference. Total resistance in ladder is 32 R. R VREF V REF = AV DD x --------------RT ( VREF + 8 ) VREF = AVDD x ----------------------------32 VREF = 0.825 + 0.103 VREF The range of internal reference in this mode is 0.825-2.37 V. RNG=1 Total resistance in ladder is 24 R. R VREF V REF = AV DD x --------------RT ( VREF ) V REF = AV DD x ------------------24 V REF = 0.1375 VREF The range of internal reference for this mode is 0.0-2.0625 V.
14.3
Initialization and Configuration
The following example shows how to configure analog comparator to read back its output value from an internal register. 1. Enable the analog comparator 0 clock by writing a value of 0x00100000 to the RCGC1 register in the System Control module. 2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input. 3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the value 0x0000030C. 4. Configure comparator 0 to use the internal voltage reference and to not output a value on the C0O pin by writing the ACCTL0 register with the value of 0x0000040C.
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5. Delay for some time. 6. Read the comparator output value by reading the ACSTAT0 register's OVAL value. Change the level of the signal input on C0- to see the OVAL value change.
14.4
Register Map
Table 14-3 lists the comparator registers. The offset listed is a hexadecimal increment to the register's address, relative to the Analog Comparator base address of 0x4003C000.
Table 14-3. Analog Comparator Register Map
Offset 0x00 0X04 0X08 0x10 0x20 0x24 Name ACMIS ACRIS ACINTEN ACREFCTL ACSTAT0 ACCTL0 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Type RO RO R/W R/W RO RW Description Interrupt status Raw interrupt status Interrupt enable Reference voltage control Comparator 0 status Comparator 0 control See page 300 301 302 303 304 305
14.5
Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset.
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Analog Comparator
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 This register provides a summary of the interrupt status (masked) of the comparator.
Analog Comparator Masked Interrupt Status (ACMIS)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
IN0
RO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. Comparator 0 Masked Interrupt Status Gives the masked interrupt state of this interrupt.
0
IN0
RO
0
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Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 This register provides a summary of the interrupt status (raw) of the comparator.
Analog Comparator Raw Interrupt Status (ACRIS)
Offset 0x04
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
IN0
RO 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. When set, indicates that an interrupt has been generated by comparator 0.
0
IN0
RO
0
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Analog Comparator
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 This register provides the interrupt enable for the comparator.
Analog Comparator Interrupt Enable (ACINTEN)
Offset 0x08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
IN0
RO R/W 0
Bit/Field 31:1
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. When set, enables the controller interrupt from the comparator 0 output.
0
IN0
R/W
0
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Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 This register specifies whether the resistor ladder is powered on as well as the range and tap.
Analog Comparator Reference Voltage Control (ACREFCTL)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved EN RNG
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W RO 0 RO R/W 0 RO 0 RO 0 RO 0 RO 0 RO R/W 0 R/W RO 0
VREF
RO R/W 0 R/W RO 0
Bit/Field 31:10
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. The EN bit specifies whether the resistor ladder is powered on. If 0, the resistor ladder is unpowered. If 1, the resistor ladder is connected to the analog VDD. This bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed.
9
EN
R/W
0
8
RNG
R/W
0
The RNG bit specifies the range of the resistor ladder. If 0, the resistor ladder has a total resistance of 32 R. If 1, the resistor ladder has a total resistance of 24 R. Reserved bits return an indeterminate value, and should never be changed. The VREF bit field specifies the resistor ladder tap that is passed through an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. See Table 14-2 on page 298 for some output reference voltage examples.
7:4
reserved
RO
0
3:0
VREF
R/W
0
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Analog Comparator
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 This register specifies the current output value of that comparator.
Analog Comparator Status 0 (ACSTAT0)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0
OVAL
RO 0
reserved
RO 0
Bit/Field 31:2
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. The OVAL bit specifies the current output value of the comparator. Reserved bits return an indeterminate value, and should never be changed.
1
OVAL
RO
0
0
reserved
RO
0
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Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x24 This register configures that comparator's input and output.
Analog Comparator Control 0 (ACCTL0)
Offset 0x024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
Type Reset
RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0
reserved
Type Reset
RO 0 RO 0 RO 0 RO 0 RO 0
ASRCP
RO R/W 0 RO R/W 0 RO 0
reserved
RO 0 RO 0 RO 0
ISLVAL
R/W RO 0 RO R/W 0
ISEN
RO R/W 0
CINV
R/W RO 0
reserved
RO RO 0
Bit/Field 31:11
Name reserved
Type RO
Reset 0
Description Reserved bits return an indeterminate value, and should never be changed. The ASRCP field specifies the source of input voltage to the VIN+ terminal of the comparator. The encodings for this field are as follows: ASRCP 00 01 10 11 Function Pin value Pin value of C0+ Internal voltage reference Reserved
10:9
ASRCP
R/W
0
8:5
reserved
RO
0
Reserved bits return an indeterminate value, and should never be changed. The ISLVAL bit specifies the sense value of the input that generates an interrupt if in Level Sense mode. If 0, an interrupt is generated if the comparator output is Low. Otherwise, an interrupt is generated if the comparator output is High. The ISEN field specifies the sense of the comparator output that generates an interrupt. The sense conditioning is as follows: ISEN 00 01 10 11 Function Level sense, see ISLVAL Falling edge Rising edge Either edge
4
ISLVAL
R/W
0
3:2
ISEN
R/W
0
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Bit/Field 1
Name CINV
Type R/W
Reset 0
Description The CINV bit conditionally inverts the output of the comparator. If 0, the output of the comparator is unchanged. If 1, the output of the comparator is inverted prior to being processed by hardware. Reserved bits return an indeterminate value, and should never be changed.
0
reserved
RO
0
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15
Pin Diagram
Figure 15-1 shows the pin diagram and pin-to-signal-name mapping. Figure 15-1. Pin Connection Diagram
PB7/TRST PB6/CCP1/C0+ PB5/C0o PB4/C0RST LDO VDD GND OSC0 OSC1 PA0/U0Rx PA1/U0Tx PA2/SSIClk PA3/SSIFss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PB3/I2CSDA PB2/I2CSCL VDD GND PB1/32KHz PB0/CCP0 GND VDD PA5/SSITx PA4/SSIRx
LM3S102
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Signal Tables
16
Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with the GPIOAFSEL register (see page 117). Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7 and PC[3:0]) which default to the JTAG functionality. Table 16-1 shows the pin-to-signal-name mapping, including functional characteristics of the signals. Table 16-2 lists the signals in alphabetical order by signal name. Table 16-3 groups the signals by functionality, except for GPIOs. Table 16-4 lists the GPIO pins and their alternate functionality.
Table 16-1. Signals by Pin Number (Sheet 1 of 2)
Pin Number 1 Signal Name PB7 TRST 2 PB6 CCP1 C0+ 3 PB5 C0o 4 PB4 C0- 5 6 7 8 9 10 11 RST LDO VDD GND OSC0 OSC1 PA0 U0Rx 12 PA1 U0Tx 13 PA2 SSIClk Pin Type I/O I I/O I/O I I/O O I/O I I I O I/O I I/O O I/O I/O Buffer Type TTL TTL TTL TTL Analog TTL TTL TTL Analog TTL Power Power Power Analog Analog TTL TTL TTL TTL TTL TTL Description GPIO port B bit 7. JTAG TAP reset input. GPIO port B bit 6. Timer 0 capture input, compare output, or PWM output port 1. Analog comparator 0 positive reference input. GPIO port B bit 5. Analog comparator 0 output. GPIO port B bit 4. Analog comparator 0 negative reference input. System reset input. The low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. Oscillator crystal input or an external clock reference input. Oscillator crystal output. GPIO port A bit 0. UART0 receive data input. GPIO port A bit 1. UART0 transmit data output. GPIO port A bit 2. SSI clock reference (input when in slave mode and output in master mode).
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Table 16-1. Signals by Pin Number (Sheet 2 of 2)
Pin Number 14 Signal Name PA3 SSIFss 15 PA4 SSIRx 16 PA5 SSITx 17 18 19 VDD GND PB0 CCP0 20 PB1 32KHz 21 22 23 GND VDD PB2 I2CSCL 24 PB3 I2CSDA 25 PC3 TDO SWO 26 PC2 TDI 27 PC1 TMS SWDIO 28 PC0 TCK SWCLK Pin Type I/O I/O I/O I I/O O I/O I/O I/O I I/O I/O I/O I/O I/O O O I/O I I/O I I/O I/O I I Buffer Type TTL TTL TTL TTL TTL TTL Power Power TTL TTL TTL TTL Power Power TTL OD TTL OD TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Description GPIO port A bit 3. SSI frame enable (input for an SSI slave device and output for an SSI master device). GPIO port A bit 4. SSI receive data input. GPIO port A bit 5. SSI transmit data output. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. GPIO port B bit 0. Timer 0 capture input, compare output, or PWM output port 0. GPIO port B bit 1. Timer clock reference input for real-time clock operation. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. GPIO port B bit 2. I2C serial clock. GPIO port B bit 3. I2C serial data. GPIO port C bit 3. JTAG scan test output. Serial-wire output. GPIO port C bit 2. JTAG scan data input. GPIO port C bit 1. JTAG mode select input. Serial-wire debug input/output. GPIO port C bit 0. JTAG scan clock reference input. Serial-wire clock reference input.
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Signal Tables
Table 16-2. Signals by Signal Name (Sheet 1 of 2)
Signal Name 32KHz C0+ C0- C0o CCP0 CCP1 GND GND GND I2CSCL I2CSDA LDO OSC0 OSC1 PA0 PA1 PA2 PA3 PA4 PA5 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Pin Number 20 2 4 3 19 2 8 18 21 23 24 6 9 10 11 12 13 14 15 16 19 20 23 24 4 3 2 1 Pin Type I I I O I/O I/O I/O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type TTL Analog Analog TTL TTL TTL Power Power Power OD OD Power Analog Analog TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Description Timer clock reference input for real-time clock operation. Analog comparator 0 positive reference input. Analog comparator 0 negative reference input. Analog comparator 0 output. Timer 0 capture input, compare output, or PWM output port 0. Timer 0 capture input, compare output, or PWM output port 1. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. I2C serial clock. I2C serial data. The low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. Oscillator crystal input or an external clock reference input. Oscillator crystal output. GPIO port A bit 0. GPIO port A bit 1. GPIO port A bit 2. GPIO port A bit 3. GPIO port A bit 4. GPIO port A bit 5. GPIO port B bit 0. GPIO port B bit 1. GPIO port B bit 2. GPIO port B bit 3. GPIO port B bit 4. GPIO port B bit 5. GPIO port B bit 6. GPIO port B bit 7.
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Table 16-2. Signals by Signal Name (Sheet 2 of 2)
Signal Name PC0 PC1 PC2 PC3 RST SSIClk SSIFss SSIRx SSITx SWCLK SWDIO SWO TCK TDI TDO TMS TRST U0Rx U0Tx VDD VDD VDD Pin Number 28 27 26 25 5 13 14 15 16 28 27 25 28 26 25 27 1 11 12 7 17 22 Pin Type I/O I/O I/O I/O I I/O I/O I O I I/O O I I O I I I O Buffer Type TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Power Power Power Description GPIO port C bit 0. GPIO port C bit 1. GPIO port C bit 2. GPIO port C bit 3. System reset input. SSI clock reference (input when in slave mode and output in master mode). SSI frame enable (input for an SSI slave device and output for an SSI master device). SSI receive data input. SSI transmit data output. Serial-wire clock reference input. Serial-wire debug input/output. Serial-wire output. JTAG scan clock reference input. JTAG scan data input. JTAG scan test output. JTAG mode select input. JTAG TAP reset input. UART0 receive data input. UART0 transmit data output. Positive supply for logic and I/O pins. Positive supply for logic and I/O pins. Positive supply for logic and I/O pins.
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Signal Tables
Table 16-3. Signals by Function, Except for GPIO (Sheet 1 of 2)
Function Analog Comparator Signal Name C0+ C0- C0o General-Purpose Timers 32KHz CCP0 CCP1 I2C I2CSCL I2CSDA JTAG/SWD/SWO SWCLK SWDIO SWO TCK TDI TDO TMS TRST Power GND GND GND LDO Pin Number 2 4 3 20 19 2 23 24 28 27 25 28 26 25 27 1 8 18 21 6 Pin Type I I O I I/O I/O I/O I/O I I/O O I I O I I Buffer Type Analog Analog TTL TTL TTL TTL OD OD TTL TTL TTL TTL TTL TTL TTL TTL Power Power Power Power Description Analog comparator 0 positive reference input. Analog comparator 0 negative reference input. Analog comparator 0 output. Timer clock reference input for real-time clock operation. Timer 0 capture input, compare output, or PWM output port 0. Timer 0 capture input, compare output, or PWM output port 1. I2C serial clock. I2C serial data. Serial wire clock reference input. Serial-wire debug input/output. Serial-wire output. JTAG scan clock reference input. JTAG scan data input. JTAG scan test output. JTAG mode select input. JTAG TAP reset input. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. The low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 F or greater. Positive supply for logic and I/O pins. Positive supply for logic and I/O pins. Positive supply for logic and I/O pins.
VDD VDD VDD
7 17 22
-
Power Power Power
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Table 16-3. Signals by Function, Except for GPIO (Sheet 2 of 2)
Function SSI Signal Name SSIClk SSIFss SSIRx SSITx System Control & Clocks OSC0 OSC1 RST UART U0Rx U0Tx Pin Number 13 14 15 16 9 10 5 11 12 Pin Type I/O I/O I O I O I I O Buffer Type TTL TTL TTL TTL Analog Analog TTL TTL TTL Description SSI clock reference (input when in slave mode and output in master mode). SSI frame enable (input for an SSI slave device and output for an SSI master device). SSI receive data input. SSI transmit data output. Oscillator crystal input or an external clock reference input. Oscillator crystal output. System reset input. UART0 receive data input. UART0 transmit data output.
Table 16-4. GPIO Pins and Alternate Functions (Sheet 1 of 2)
GPIO Pin PA0 PA1 PA2 PA3 PA4 PA5 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 Pin Number 11 12 13 14 15 16 19 20 23 24 4 3 2 1 28 Multiplexed Function U0Rx U0Tx SSIClk SSIFss SSIRx SSITx CCP0 32KHz I2CSCL I2CSDA C0C0o C0+ TRST TCK SWCLK CCP1 Multiplexed Function
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Signal Tables
Table 16-4. GPIO Pins and Alternate Functions (Sheet 2 of 2)
GPIO Pin PC1 PC2 PC3 Pin Number 27 26 25 Multiplexed Function TMS TDI TDO SWO Multiplexed Function SWDIO
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17
Operating Characteristics
Table 17-1. Temperature Characteristics
Characteristic Operating temperature rangea Symbol TA Value -40 to +85 for industrial Unit C
a. Maximum storage temperature is 150C.
Table 17-2. Thermal Characteristics
Characteristic Thermal resistance (junction to ambient)a Average junction temperatureb Maximum junction temperature Symbol JA TJ TJMAX Value 74 TA + (PAVG * JA) pendingc Unit C/W C C
a. Junction to ambient thermal resistance JA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. c. Pending characterization completion.
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Electrical Characteristics
18
18.1
18.1.1
Electrical Characteristics
DC Characteristics
Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 18-1. Maximum Ratings
Characteristica Supply voltage range (VDD) Input voltage Maximum current for pins, excluding pins operating as GPIOs Maximum current for GPIO pins
a. Voltages are measured with respect to GND.
Symbol VDD VIN I I
Value 0.0 to +3.6 -0.3 to 5.5 100 100
Unit V V mA mA
Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either GND or VDD).
18.1.2
Recommended DC Operating Conditions
Table 18-2. Recommended DC Operating Conditions
Parameter VDD VIH VIL VSIH VSIL VOH VOL Parameter Name Supply voltage High-level input voltage Low-level input voltage High-level input voltage for Schottky inputs Low-level input voltage for Schottky inputs High-level output voltage Low-level output voltage Min 3.0 2.0 -0.3 0.8 * VDD 0 2.4 Nom 3.3 Max 3.6 5.0 1.3 VDD 0.2 * VDD 0.4 Unit V V V V V V V
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Table 18-2. Recommended DC Operating Conditions (Continued)
Parameter IOH Parameter Name High-level source current, VOH=2.4 V 2-mA Drive 4-mA Drive 8-mA Drive IOL Low-level sink current, VOL=0.4 V 2-mA Drive 4-mA Drive 8-mA Drive 2.0 4.0 8.0 mA mA mA 2.0 4.0 8.0 mA mA mA Min Nom Max Unit
18.1.3
On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 18-3. LDO Regulator Characteristics
Parameter VLDOOUT Parameter Name Programmable internal (logic) power supply output value Output voltage accuracy tPON tON tOFF VSTEP CLDO Power-on time Time on Time off Step programming incremental voltage External filter capacitor size for internal power supply Min 2.25 Nom 2% 50 1 Max 2.75 100 200 100 Unit V % s s s mV F
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Electrical Characteristics
18.1.4
Power Specifications
The power measurements specified in Table 18-4 are run on the core processor using SRAM with the following specifications: VDD=3.3 V LDO=2.5 Temperature=25C System Clock=20 MHz (with PLL) Code while(1){} executed from SRAM with no active peripherals
Table 18-4. Power Specifications
Parameter IDD_RUN IDD_SLEEP IDD_DEEPSLEEP Parameter Name Run mode Sleep mode Deep-Sleep mode Min Nom 35a pendinga pendinga Max pendinga pendinga pendinga Unit mA A A
a. Pending characterization completion.
18.1.5
Flash Memory Characteristics
Table 18-5. Flash Memory Characteristics
Parameter PECYC TRET TPROG TERASE TME Parameter Name Number of guaranteed program/erase cyclesa before failure Data retention at average operating temperature of 85C Word program time Page erase time Mass erase time Min 10,000 10 20 20 200 Nom Max Unit cycles years s ms ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
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18.2
18.2.1
AC Characteristics
Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing measurements are for 4-mA drive strength. Figure 18-1. Load Conditions
pin
CL = 50 pF
GND
18.2.2
Clocks
Table 18-6. Phase Locked Loop (PLL) Characteristics
Parameter fREF_CRYSTAL fREF_EXT fPLL TREADY Parameter Name Crystal referencea External clock referencea PLL frequencyb PLL lock time Min 3.579545 3.579545 Nom 200 Max 8.192 8.192 0.5 Unit MHz MHz MHz ms
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register (see page 74). b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 18-7. Clock Characteristics
Parameter fIOSC fMOSC tMOSC_PER fREF_CRYSTAL_BYPASS Parameter Name Internal oscillator frequency Main oscillator frequency Main oscillator period Crystal reference using the main oscillator (PLL in BYPASS mode) External clock reference (PLL in BYPASS mode) System clock Min 7 1 125 1 Nom 15 Max 22 8 1000 8 Unit MHz MHz ns MHz
fREF_EXT_BYPASS fSYSTEM_CLOCK
0 0
-
20 20
MHz MHz
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Electrical Characteristics
18.2.3
Analog Comparator
Table 18-8. Analog Comparator Characteristics
Parameter VOS VCM CMRR TRT TMC Parameter Name Input offset voltage Input common mode voltage range Common mode rejection ratio Response time Comparator mode change to Output Valid Min 0 50 Nom 10 Max 25 VDD-1.5 1 10 Unit mV V dB s s
Table 18-9. Analog Comparator Voltage Reference Characteristics
Parameter RHR RLR AHR ALR Parameter Name Resolution high range Resolution low range Absolute accuracy high range Absolute accuracy low range Min Nom VDD/32 VDD/24 Max 1/2 1/4 Unit LSB LSB LSB LSB
18.2.4
I2C
I2C Characteristics
Parameter tSCH tLP tSRT tDH tSFT tHT tDS Parameter Name Start condition hold time Clock Low period I2CSCL/I2CSDA rise time (VIL=0.5 V to VIH=2.4 V) Data hold time I2CSCL/I2CSDA fall time (VIH=2.4 V to VIL=0.5 V) Clock High time Data setup time Min 36 36 2 24 18 Nom 9 Max (see note b) 10 Unit system clocks system clocks ns system clocks ns system clocks system clocks
Table 18-10.
Parameter No. I1a I2a I3b I4a I5c I6a I7a
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Table 18-10.
Parameter No. I8a I9a
I2C Characteristics (Continued)
Parameter tSCSR tSCS Parameter Name Start condition setup time (for repeated start condition only) Stop condition setup time Min 36 24 Nom Max Unit system clocks system clocks
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register (see page 282); a TPR programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table above. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 18-2.
I2C Timing
I2 I6 I5
I2CSCL
I1 I4 I7 I8 I3
I2CSDA
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Electrical Characteristics
18.2.5
Synchronous Serial Interface (SSI)
Table 18-11. SSI Characteristics
Parameter No. S1 S2 S3 S4 S5 S6 S7 S8 S9 Parameter tCLK_PER tCLK_HIGH tCLK_LOW tCLKRF tDMD tDMS tDMH tDSS tDSH Parameter Name SSIClk cycle time SSIClk high time SSIClk low time SSIClk rise/fall time Data from master valid delay time Data from master setup time Data from master hold time Data from slave setup time Data from slave hold time Min 2 0 20 40 20 40 Nom 1/2 1/2 7.4 Max 65024 26 20 Unit system clocks tCLK_PER tCLK_PER ns ns ns ns ns ns
Figure 18-3.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
S1 S2 S4
SSIClk
S3
SSIFss SSITx SSIRx
MSB
4 to 16 bits
LSB
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Figure 18-4.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
S2 S1
SSIClk
S3
SSIFss
SSITx
MSB 8-bit control
LSB
SSIRx
0
MSB 4 to 16 bits output data
LSB
Figure 18-5.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1
S1 S4 S2
SSIClk (SPO=0)
S3
SSIClk (SPO=1)
S6 S7
SSITx (master)
S5
MSB
S8 S9
LSB
SSIRx (slave) SSIFss
MSB
LSB
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Electrical Characteristics
18.2.6
JTAG and Boundary Scan
JTAG Characteristics
Parameter fTCK tTCK tTCK_LOW tTCK_HIGH tTCK_R tTCK_F tTMS_SU tTMS_HLD tTDI_SU tTDI_HLD TCK fall to Data Valid from High-Z Parameter Name TCK operational clock frequency TCK operational clock period TCK clock Low time TCK clock High time TCK rise time TCK fall time TMS setup time to TCK rise TMS hold time from TCK rise TDI setup time to TCK rise TDI hold time from TCK rise 2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control Min 0 100 0 0 20 20 25 25 Nom 1/2 tTCK 1/2 tTCK 23 15 14 18 21 14 13 18 9 7 6 7 100 10 Max 10 10 10 35 26 25 29 35 25 24 28 11 9 8 9 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 18-12.
Parameter No. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 tTDO_ZDV
J12 tTDO_DV
TCK fall to Data Valid from Data Valid
2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control
J13 tTDO_DVZ
TCK fall to High-Z from Data Valid
2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control
J14 J15
tTRST tTRST_SU
TRST assertion time TRST setup time to TCK rise
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LM3S102 Data Sheet
Figure 18-6.
JTAG Test Clock Input Timing
J2 J3 J4
TCK
J6 J5
Figure 18-7.
JTAG Test Access Port (TAP) Timing
TCK
J7 J8 J7 J8
TMS
TMS Input Valid J9 J10
TMS Input Valid J9 J10
TDI
J11
TDI Input Valid J12 TDO Output Valid
TDI Input Valid J13 TDO Output Valid
TDO
Figure 18-8. JTAG TRST Timing
TCK
J14 J15
TRST
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Electrical Characteristics
18.2.7
General-Purpose I/O
GPIO Characteristicsa
Parameter Name GPO Rise Time (from 20% to 80% of VDD) Condition 2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control Min Nom 17 9 6 10 17 8 6 11 Max 26 13 9 12 25 12 10 13 Unit ns ns ns ns ns ns ns ns
Table 18-13.
Parameter tGPIOR
tGPIOF
GPO Fall Time (from 80% to 20% of VDD)
2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control
a. All GPIOs are 5 V-tolerant.
18.2.8
Reset
Reset Characteristics
Parameter VTH VBTH TPOR TBOR TIRPOR TIRBOR TIRHWR TIRSWR TIRWDR TIRLDOR TVDDRISE Parameter Name Reset threshold Brown-Out threshold Power-On Reset timeout Brown-Out timeout Internal reset timeout after POR Internal reset timeout after BORa Internal reset timeout after hardware reset (RST pin) Internal reset timeout after software-initiated system reseta Internal reset timeout after watchdog reseta Internal reset timeout after LDO reseta Supply voltage (VDD) rise time (0V-3.3V) Min 2.85 15 2.5 15 2.5 2.5 2.5 Nom 2.0 2.9 10 500 Max 2.95 30 20 30 20 20 20 100 Unit V V ms s ms s ms s s s ms
Table 18-14.
Parameter No. R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11
a. 20 * tMOSC_PER
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Figure 18-9.
External Reset Timing (RST)
RST
R7
/Reset (Internal)
Figure 18-10. Power-On Reset Timing
R1
VDD
R3
/POR (Internal)
R5
/Reset (Internal)
Figure 18-11. Brown-Out Reset Timing
R2
VDD
R4
/BOR (Internal)
R6
/Reset (Internal)
Figure 18-12. Software Reset Timing
SW Reset
R8
/Reset (Internal)
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Electrical Characteristics
Figure 18-13.
Watchdog Reset Timing
WDT Reset (Internal) /Reset (Internal)
Figure 18-14. LDO Reset Timing
R9
LDO Reset (Internal)
R10
/Reset (Internal)
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LM3S102 Data Sheet
19
Package Information
28-Pin SOIC Package
Figure 19-1.
NOTES:
1. Dimension "D" does not include mold flash, protrusions, or gate burrs. MOld flash, protrusions, and gate burrs shall not exceed .006" (0.15mm) per side. Dimension "E" does not include inter-lead flash or protrusions. Interlead flash and protrusion shall not exceed ".010" (0.25 mm) per side. "L" is the length of terminal for soldering to a substrate. "N" is the number of terminal positions. Terminal numbers are shown for reference only. The lead width "b", as measured .014" (0.36 mm) or greater above the seating plane, shall not exceed a maximum value of .024" (0.61 mm). Reference drawing JEDEC MS013, Variation AE.
DIMENSION IN INCH DIMENSION IN MM SYMBOL MIN A A1 B C D E e H h L S .093 .004 .013 .009 .696 .291 .394 .010 .016 .021 0 MAX .014 .012 .020 .013 .713 .299 .419 .029 .050 .031 8 MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 0.533 0 MAX 2.65 0.30 0.51 .032 18.10 7.60 10.65 0.75 1.27 .0787 8
2. 3. 4. 5. 6.
7.
0.50 BSC
1.27 BSC
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Appendix A. Serial Flash Loader
The Stellaris serial flash loader is used to download code to the flash memory of a device without the use of a debug interface. The serial flash loader uses a simple packet interface to provide synchronous communication with the device. The flash loader runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used. The two serial interfaces that can be used are the UART0 and SSI interfaces. For simplicity, both the data format and communication protocol are identical for both serial interfaces.
A.1
Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface is used until the flash loader is reset or new code takes over. For example, once you start communicating using the SSI port, communications with the flash loader via the UART are disabled until the device is reset.
A.1.1
UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is automatically detected by the flash loader and can be any valid baud rate supported by the host and the device. The auto detection sequence requires that the baud rate should be no more than 1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device. In order to determine the baud rate, the serial flash loader needs to determine the relationship between its own crystal frequency and the baud rate. This is enough information for the flash loader to configure its UART to the same baud rate as the host. This automatic baud rate detection allows the host to use any valid baud rate that it wants to communicate with the device. The method used to perform this automatic synchronization relies on the host sending the flash loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can use to calculate the ratios needed to program the UART to match the host's baud rate. After the host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has received a synchronization pattern correctly. For example, the time to wait for data back from the flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate of 115200, this time is 2*(20/115200) or 0.35ms.
A.1.2
SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications, with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See the section on SSI formats for more details on this transfer protocol. Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running the flash loader. Since the host device is the master, the SSI on the flash loader device does not need to determine the clock as it is provided directly by the host.
A.2
Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
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format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet.
A.2.1
Packet Format
All packets sent and received from the device use the following byte-packed format.
struct { unsigned char ucSize; unsigned char ucCheckSum; unsigned char Data[]; };
ucSize - The first byte received holds the total size of the transfer including the size and checksum bytes. ucChecksum - This holds a simple checksum of the bytes in the data buffer only. The algorithm is Data[0]+Data[1]+...+ Data[ucSize-3]. Data - This is the raw data intended for the device, which is formatted in some form of command interface. There should be ucSize - 2 bytes of data provided in this buffer to or from the device.
A.2.2
Sending Packets
The actual bytes of the packet can be sent individually or all at once, the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. This limitation is discussed further in the commands that interact with the flash. Once the packet has been formatted correctly by the host, it should be sent out over the UART or SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This does not indicate that the actual contents of the command issued in the data portion of the packet were valid, just that the packet was received correctly.
A.2.3
Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. There is no break in the data after the first non-zero byte is sent from the flash loader. Once the device communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to indicate that the transmission was successful. The appropriate response after sending a NAK to the flash loader is to resend the command that failed and request the data again. If needed, the host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the flash loader only accepts the first non-zero data as a valid response. This zero padding is needed by the SSI interface in order to receive data to or from the flash loader.
A.3
Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent.
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A.3.1
COMMAND_PING (0x20)
This command simply accepts the command and sets the global status to success. The format of the packet is as follows:
Byte[0] = 0x03; Byte[1] = checksum(Byte[2]); Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status, the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.3.2
COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. The command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. The last step is to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_GET_STATUS
A.3.3
COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit values that are both transferred MSB first. The first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent. This command also triggers an erase of the full area to be programmed so this command takes longer than other commands. This results in a longer time to receive the ACK/NAK back from the board. This command should be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size are valid for the device running the flash loader. The format of the packet to send this command is a follows:
Byte[0] = 11 Byte[1] = checksum(Bytes[2:10]) Byte[2] = COMMAND_DOWNLOAD Byte[3] = Program Address [31:24] Byte[4] = Program Address [23:16] Byte[5] = Program Address [15:8] Byte[6] = Program Address [7:0] Byte[7] = Program Size [31:24] Byte[8] = Program Size [23:16] Byte[9] = Program Size [15:8] Byte[10] = Program Size [7:0]
A.3.4
COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
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LM3S102 Data Sheet
automatically increment address and continue programming from the previous location. The caller should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program successfully and not overflow input buffers of the serial interfaces. The command terminates programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK to this command, the flash loader does not increment the current address to allow retransmission of the previous data.
Byte[0] = 11 Byte[1] = checksum(Bytes[2:10]) Byte[2] = COMMAND_SEND_DATA Byte[3] = Data[0] Byte[4] = Data[1] Byte[5] = Data[2] Byte[6] = Data[3] Byte[7] = Data[4] Byte[8] = Data[5] Byte[9] = Data[6] Byte[10] = Data[7]
A.3.5
COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter in this command. This command consists of a single 32-bit value that is interpreted as the address to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK signal back to the host device before actually executing the code at the given address. This allows the host to know that the command was received successfully and the code is now running.
Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6]
= = = = = = =
7 checksum(Bytes[2:6]) COMMAND_RUN Execute Address[31:24] Execute Address[23:16] Execute Address[15:8] Execute Address[7:0]
A.3.6
COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a new image that overwrote the flash loader and wants to start from a full reset. Unlike the COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set up for the new code. It can also be used to reset the flash loader if a critical error occurs and the host device wants to restart communication with the flash loader.
Byte[0] = 3 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the software reset to the device running the flash loader. This allows the host to know that the command was received successfully and the part will be reset.
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Ordering and Contact Information
Ordering Information
Features ADC Samples Per Second # of 10-Bit Channels Analog Comparator(s) PWMc Speed (Clock Frequency in MHz) 20 Operating Temperatured I
SRAM (KB)
Flash (KB)
PWM Pins
CCP Pins
LM3S102-IRN20 LM3S102-IRN20(T)
a. b. c. d. e. f.
f
8
2
0 to 18
2
-
-
1
1
-
2
QEI
SSI
Order Number
-
Minimum is number of pins dedicated to GPIO; additional pins are available if certain peripherals are not used. See data sheet for details. One timer available as RTC. PWM motion control functionality can be achieved through dedicated motion control hardware (using the PWM pins) or through the motion control features of the general-purpose timers (using the CCP pins). See data sheet for details. I=Industrial (-40 to 85C). RN=28-pin RoHS-compliant SOIC. T=Tape and Reel.
Development Kit
The Luminary Micro StellarisTM Family Development Kit provides the hardware and software tools that engineers need to begin development quickly. Ask your Luminary Micro distributor for part number DK-LM3S102. See the Luminary Micro website for the latest tools available.
Packagee RN
UART(s)
Timersb
GPIOsa
I2C
Tools to begin development quickly
Company Information
Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3 based microcontrollers for use in embedded applications within the industrial, commercial, and consumer markets. Luminary Micro is ARM's lead partner in the implementation of the Cortex-M3 core. Please contact us if you are interested in obtaining further information about our company or our products. Luminary Micro, Inc. 2499 South Capital of Texas Hwy, Suite A-100 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com sales@luminarymicro.com
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Support Information
For support on Luminary Micro products, contact: support@luminarymicro.com +1-512-279-8800, ext. 3
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